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amdgpu/addrlib: add tcCompatible htile addr from coordinate support.
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parent
3bd1380ab2
commit
6164f23a91
5 changed files with 80 additions and 13 deletions
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@ -851,6 +851,7 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
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UINT_32 slice; ///< Index of slice
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UINT_32 numSlices; ///< Number of slices
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BOOL_32 isLinear; ///< Linear or tiled HTILE layout
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ADDR_HTILE_FLAGS flags; ///< htile flags
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AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
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AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
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ADDR_TILEINFO* pTileInfo; ///< Tile info
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@ -859,6 +860,8 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
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/// while the global useTileIndex is set to 1
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INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
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///< README: When tileIndex is not -1, this must be valid
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UINT_32 bpp; ///< depth/stencil buffer bit per pixel size
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UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address
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} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
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/**
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@ -1422,18 +1422,25 @@ ADDR_E_RETURNCODE AddrLib1::ComputeHtileAddrFromCoord(
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if (returnCode == ADDR_OK)
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{
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pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch,
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pIn->height,
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pIn->x,
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pIn->y,
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pIn->slice,
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pIn->numSlices,
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1,
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pIn->isLinear,
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isWidth8,
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isHeight8,
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pIn->pTileInfo,
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&pOut->bitPosition);
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if (pIn->flags.tcCompatible)
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{
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HwlComputeHtileAddrFromCoord(pIn, pOut);
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}
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else
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{
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pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch,
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pIn->height,
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pIn->x,
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pIn->y,
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pIn->slice,
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pIn->numSlices,
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1,
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pIn->isLinear,
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isWidth8,
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isHeight8,
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pIn->pTileInfo,
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&pOut->bitPosition);
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}
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}
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}
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@ -290,6 +290,14 @@ protected:
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return ADDR_NOTSUPPORTED;
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}
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/// Virtual function to get htile address for tc compatible htile
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virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
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const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const
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{
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return ADDR_NOTSUPPORTED;
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}
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// Compute attributes
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// HTILE
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@ -308,7 +308,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeCmaskAddrFromCoord(
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UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(fmaskAddress,
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0,
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0,
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4,
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4, // cmask 4 bits
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elemBits,
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blockByte,
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m_pipeInterleaveBytes,
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@ -322,6 +322,51 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeCmaskAddrFromCoord(
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return returnCode;
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}
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/**
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***************************************************************************************************
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* CiAddrLib::HwlComputeHtileAddrFromCoord
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*
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* @brief
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* Compute tc compatible Htile address from depth/stencil address
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*
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* @return
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* ADDR_E_RETURNCODE
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***************************************************************************************************
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*/
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ADDR_E_RETURNCODE CiAddrLib::HwlComputeHtileAddrFromCoord(
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const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, ///< [in] depth/stencil addr/bpp/tile input
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ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut ///< [out] htile address
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) const
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{
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ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED;
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if ((m_settings.isVolcanicIslands == TRUE) &&
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(pIn->flags.tcCompatible == TRUE))
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{
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UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo);
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UINT_32 numOfBanks = pIn->pTileInfo->banks;
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UINT_64 zStencilAddr = pIn->zStencilAddr;
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UINT_32 elemBits = pIn->bpp;
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UINT_32 blockByte = 64 * elemBits / 8;
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UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(zStencilAddr,
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0,
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0,
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32, // htile 32 bits
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elemBits,
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blockByte,
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m_pipeInterleaveBytes,
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numOfPipes,
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numOfBanks,
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1);
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pOut->addr = (metaNibbleAddress >> 1);
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pOut->bitPosition = 0;
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returnCode = ADDR_OK;
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}
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return returnCode;
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}
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/**
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***************************************************************************************************
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* CiAddrLib::HwlConvertChipFamily
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@ -154,6 +154,10 @@ protected:
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const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
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const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
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virtual VOID HwlPadDimensions(
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