fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 19:30:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

amdgpu/addrlib: Refine the PRT tile mode selection

Browse source 
Switch the tile index based on logic instead of hardcoded threshold
for different ASIC.
This commit is contained in:
Frans Gu 2014-12-03 05:47:09 -05:00 • committed by Marek Olšák
parent 2bf243f7c6
commit ca6a38fd6a
2 changed files with 19 additions and 51 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

68
src/amd/addrlib/r800/ciaddrlib.cpp
View file

@ -910,49 +910,6 @@ BOOL_32 CiAddrLib::HwlOverrideTileMode(
return bOverrided;
}
/**
***************************************************************************************************
* CiAddrLib::GetPrtSwitchP4Threshold
*
* @brief
* Return the threshold of switching to P4_* instead of P16_* for PRT resources
***************************************************************************************************
*/
UINT_32 CiAddrLib::GetPrtSwitchP4Threshold() const
{
UINT_32 threshold;
switch (m_pipes)
{
case 8:
threshold = 32;
break;
case 16:
if (m_settings.isFiji)
{
threshold = 16;
}
else if (m_settings.isHawaii)
{
threshold = 8;
}
else
{
///@todo add for possible new ASICs.
ADDR_ASSERT_ALWAYS();
threshold = 16;
}
break;
default:
///@todo add for possible new ASICs.
ADDR_ASSERT_ALWAYS();
threshold = 32;
break;
}
return threshold;
}
/**
***************************************************************************************************
* CiAddrLib::HwlSetupTileInfo
@ -1185,16 +1142,29 @@ VOID CiAddrLib::HwlSetupTileInfo(
ADDR_ASSERT((index + 1) < static_cast<INT_32>(m_noOfEntries));
// Only do this when tile mode table is updated.
if (((tileMode == ADDR_TM_PRT_TILED_THIN1) || (tileMode == ADDR_TM_PRT_TILED_THICK)) &&
(m_tileTable[index+1].mode == tileMode))
(m_tileTable[index + 1].mode == tileMode))
{
UINT_32 bytesXSamples = bpp * numSamples / 8;
UINT_32 bytesXThickness = bpp * thickness / 8;
UINT_32 switchP4Threshold = GetPrtSwitchP4Threshold();
static const UINT_32 PrtTileBytes = 0x10000;
ADDR_TILEINFO tileInfo = {0};
if ((bytesXSamples > switchP4Threshold) || (bytesXThickness > switchP4Threshold))
HwlComputeMacroModeIndex(index, flags, bpp, numSamples, &tileInfo);
UINT_32 macroTileBytes = (bpp >> 3) * 64 * numSamples * thickness *
HwlGetPipes(&tileInfo) * tileInfo.banks *
tileInfo.bankWidth * tileInfo.bankHeight;
if (macroTileBytes != PrtTileBytes)
{
// Pick next 4 pipe entry
// Switching to next tile mode entry to make sure macro tile size is 64KB
index += 1;
tileInfo.pipeConfig = m_tileTable[index].info.pipeConfig;
macroTileBytes = (bpp >> 3) * 64 * numSamples * thickness *
HwlGetPipes(&tileInfo) * tileInfo.banks *
tileInfo.bankWidth * tileInfo.bankHeight;
ADDR_ASSERT(macroTileBytes == PrtTileBytes);
}
}
}

2
src/amd/addrlib/r800/ciaddrlib.h
View file

@ -169,8 +169,6 @@ private:
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
UINT_32 GetPrtSwitchP4Threshold() const;
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);