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amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled
Experiment show 1D tiling + TcCompatible cannot work together.
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1 changed files with 21 additions and 18 deletions
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@ -1317,30 +1317,33 @@ VOID CiAddrLib::HwlSetupTileInfo(
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*pTileInfo = m_tileTable[8].info;
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}
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// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil is
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// handled at tileIndex selecting time.
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if (pOut->tcCompatible && (inTileType != ADDR_DEPTH_SAMPLE_ORDER))
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if (pOut->tcCompatible)
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{
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if (IsMacroTiled(tileMode))
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{
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INT_32 tileIndex = pOut->tileIndex;
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if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
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if (inTileType != ADDR_DEPTH_SAMPLE_ORDER)
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{
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tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
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}
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// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
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// tileSplit case was handled at tileIndex selecting time.
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INT_32 tileIndex = pOut->tileIndex;
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if (tileIndex != TileIndexInvalid)
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{
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ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
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// Non-depth entries store a split factor
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UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
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UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
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UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
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if (m_rowSize < colorTileSplit)
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if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
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{
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pOut->tcCompatible = FALSE;
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tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
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}
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if (tileIndex != TileIndexInvalid)
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{
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ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
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// Non-depth entries store a split factor
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UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
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UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
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UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
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if (m_rowSize < colorTileSplit)
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{
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pOut->tcCompatible = FALSE;
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}
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}
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}
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}
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