amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled

Experiment show 1D tiling + TcCompatible cannot work together.
This commit is contained in:
Roy Zhan 2015-06-09 04:46:59 -04:00 committed by Marek Olšák
parent 120a5d0e42
commit 554c1b9f2d

View file

@ -1317,30 +1317,33 @@ VOID CiAddrLib::HwlSetupTileInfo(
*pTileInfo = m_tileTable[8].info;
}
// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil is
// handled at tileIndex selecting time.
if (pOut->tcCompatible && (inTileType != ADDR_DEPTH_SAMPLE_ORDER))
if (pOut->tcCompatible)
{
if (IsMacroTiled(tileMode))
{
INT_32 tileIndex = pOut->tileIndex;
if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
if (inTileType != ADDR_DEPTH_SAMPLE_ORDER)
{
tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
}
// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
// tileSplit case was handled at tileIndex selecting time.
INT_32 tileIndex = pOut->tileIndex;
if (tileIndex != TileIndexInvalid)
{
ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
// Non-depth entries store a split factor
UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
if (m_rowSize < colorTileSplit)
if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
{
pOut->tcCompatible = FALSE;
tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
}
if (tileIndex != TileIndexInvalid)
{
ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
// Non-depth entries store a split factor
UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
if (m_rowSize < colorTileSplit)
{
pOut->tcCompatible = FALSE;
}
}
}
}