Commit graph

13968 commits

Author SHA1 Message Date
Caio Oliveira
89f0db0aaa brw: Remove extra interface in brw_cfg types
The C++ one is more used, so let that one remain.  These data structures
are not used from C sources anymore.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33957>
2025-03-10 19:23:17 +00:00
Lionel Landwerlin
1835bf3520 brw: avoid calling lower_indirect_derefs multiple times
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Lowering the indirect derefs multiple times leads to very inefficient
shaders because of all the control flow inserted.

In particular on some DGC tests with mesh shaders, the tests can spin
for 1hour on an i7 and still not complete compilation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33809>
2025-03-09 20:52:01 +00:00
Guilherme Gallo
4a2717c4bd ci: Specify the FARM variable for DUT jobs
There are some jobs that were missing the FARM variable, which is useful
to lava_job_submitter.py to classify how it should interact with each
LAVA server and how it should assemble the job definition.
Right now, we use a set of regexex with the RUNNER_TAG variable, but
that is error-prone.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33888>
2025-03-08 02:45:02 +00:00
Sagar Ghuge
1bfe2571f5 intel/compiler: Lower sample index into coord for MSRT messages
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32690>
2025-03-07 23:06:14 +00:00
Sagar Ghuge
bea9d79cb9 intel/compiler: Add support for MSAA typed load/store messages
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32690>
2025-03-07 23:06:14 +00:00
Caio Oliveira
ff59013571 brw: Rework label tracking in assembler
For each label store its offset and two lists of uses (for JIP and UIP).
Because the parser itself already restricts what opcodes can use labels
(and which ones), don't re-validate them.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33522>
2025-03-06 17:06:20 -08:00
Caio Oliveira
7b45d31df0 brw: Add support for GOTO/JOIN in the assembler
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33522>
2025-03-06 17:06:20 -08:00
Caio Oliveira
9df254731e brw: Make assembler strict about JIP and UIP order
The "JIP:" and "UIP:" markers were being ignored, so was possible
to switch their order in the text but the parser would act as the
same.  Just fix the order now and enforce it through the parsing.

Since we are here, remove the "Jump:" and "Pop:" that are not used
for Gfx9+ anymore.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33522>
2025-03-06 17:06:19 -08:00
Caio Oliveira
25875f5e79 brw: Remove bblock_t parameters from various passes
These are either unused or can be trivially replaced by
a block stored in an instruction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
8e2a7cb42d brw: Embed at_end() inside brw_builder(brw_shader *) constructor
All remaining uses of that constructor would also use at_end(),
and vice-versa.  So just implement that behavior in the constructor
itself.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
6f37e6f104 brw: Add explicit way to get an empty brw_builder
And use brw_builder(brw_shader *) and brw_builder() constructors
where possible.

The way tests are written, it is necessary to initialize an "empty"
builder -- which is later replaced by a proper one.  Default parameter
NULL make that initialization implicit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
32e562ae01 brw: Simplify brw_builder "insert before inst" constructor
Since brw_inst now has the block it belongs and the block can
reach the shader, the only necessary information to create a
builder is the brw_inst itself.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
66307811c3 brw: Remove block parameter from brw_inst::remove()
Use brw_inst::block instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
7924d48bcd brw: Use brw_inst::block in CSE
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
b0b0fa8624 brw: Use brw_inst::block in Combine Constants
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
07d0af763d brw: Use brw_inst::block in Def analysis
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
705d448bc3 brw: Add block pointer in brw_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
Caio Oliveira
b71ec53048 brw: Remove unused function
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>
2025-03-06 23:33:38 +00:00
José Roberto de Souza
a13a6656dd intel: Add function to check if PXP is supported in Xe KMD
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30723>
2025-03-06 16:25:04 +00:00
José Roberto de Souza
e146e573f7 anv: Add support to create protected bo and protected exec_queue in Xe KMD
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30723>
2025-03-06 16:25:03 +00:00
José Roberto de Souza
a99d90d015 anv: Move code adding protected memory type to common code
Xe KMD now has support for protected memory, so lets move it
to common code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30723>
2025-03-06 16:25:03 +00:00
José Roberto de Souza
4860532f49 anv: Remove protected memory support from compute queue
CCS don't support MI_SET_APPID instruction, that might be the reason
some tests protected memory tests fail on CCS.
Re-enable it if a workaround/solution is found.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30723>
2025-03-06 16:25:03 +00:00
José Roberto de Souza
008ac818ba intel/common: Retry GEM_CONTEXT_CREATE when PXP have not finished initialization
If PXP initialization is not completed and application requested a
protected context the GEM_CONTEXT_CREATE will wait up to 250ms for
PXP to finish initialization but if that do not happens it will
return a error and set errno to EIO.
This patch add the missing retry handling.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30723>
2025-03-06 16:25:03 +00:00
Alyssa Rosenzweig
c0022b6603 intel: use common CL args
this contains two behaviour changes:

* NDEBUG no longer set in debug builds (so asserts work in debug, but are still
  stripped out in release as expected).
* macro map set properly for assertions to be reported with proper paths.

together this makes assertions do the right thing on Intel and brings us in
alignment with asahi+panfrost

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
2025-03-06 00:43:59 +00:00
Caio Oliveira
54912281a0 brw: Always verify EU compaction in debug mode
There's already code to verify that any compacted instruction
that we produce is equivalent to the original uncompacted
instruction -- including detailed output if it fails.

This patch enables this verification in debug build and will
abort in case it fails.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33821>
2025-03-06 00:14:14 +00:00
Lionel Landwerlin
199a052481 anv: fixup indentation around Wa_16014912113
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:12 +00:00
Lionel Landwerlin
888b2ec7b0 anv: break down Wa_16014912113 in need/apply parts
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:12 +00:00
Lionel Landwerlin
93a327c4e6 anv/brw: move INTEL_MSAA_* flag computation to the compiler
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:12 +00:00
Lionel Landwerlin
beaba53010 brw: make intel_shader_enums.h opencl importable
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:12 +00:00
Lionel Landwerlin
02eb26de0a genxml: simplify genX_rt_pack.h
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:11 +00:00
Lionel Landwerlin
374d2168ee intel/genxml: add a genX RT include header
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:11 +00:00
Lionel Landwerlin
17ba9a19d1 anv/apply_layout: split binding table building into its own function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
2025-03-05 17:20:11 +00:00
Michael Cheng
014f376755 anv: Change as_build to show num tlas/blas
As_build now shows the number of tlas/blas that was built.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33720>
2025-03-05 14:19:56 +00:00
Tapani Pälli
1674cb3665 anv: restrict TessellationDistributionLevel for Wa_16025857284
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33864>
2025-03-05 09:55:05 +00:00
Tapani Pälli
1a5cbbeb47 intel/dev: update mesa_defs.json from internal database
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33864>
2025-03-05 09:55:05 +00:00
Lucas Fryzek
b37bcd01ed anv: Expose VK_EXT_device_memory_report
Also mark VK_EXT_device_memory_report as supported by anv in
docs/features.txt

Co-authored-by: shenghualin <shenghua.lin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33767>
2025-03-04 15:24:39 +00:00
Lucas Fryzek
f01ad7c34c anv: Implement VK_EXT_device_memory_report
Report device memory events for:
  - command buffers
  - pipelines
  - descriptor sets and descriptor pools
  - device memory

Co-authored-by: shenghualin <shenghua.lin@intel.com>
Co-authored-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33767>
2025-03-04 15:24:39 +00:00
Caio Oliveira
dd1ca1588d brw: Fix size in assembler when compacting
Calculation was wrongly walking uncompacted instructions, even if we had
some compacted in the middle, generating invalid size.  Since we are
here just drop the instruction count, since in practice the caller will
have to walk the instruction stream anyway.

Fixes: 6267585778 ("intel/brw: Also return the size of the assembled shader")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33532>
2025-03-03 20:43:56 +00:00
Lucas Fryzek
08483e9bfa anv: Release correct bo for RT scratch
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33850>
2025-03-03 20:13:38 +00:00
Hyunjun Ko
f80e5c2ce5 anv/ci: remove some expected failures of dEQP-VK.video.formats.*
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33784>
2025-03-03 04:36:21 +00:00
Hyunjun Ko
f7ff9b240d anv: Do not support the tiling of DRM modifier if DECODE_DST
Fixes: 04709e4f ("anv: fix video profile lists");

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33784>
2025-03-03 04:36:21 +00:00
Alyssa Rosenzweig
0b4ccac83e anv,hasvk: switch to common VK_COPY/PRINT_STR
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33826>
2025-03-01 20:27:26 +00:00
Mike Blumenkrantz
6a29d2ed66 anv: support all dimensions of image for LINEAR dmabufs
> Allowing 1D and 3D images, and array images too, with DRM_FORMAT_MOD_LINEAR, is ok
> because VkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts is able to fully
> describe the image layout. IF miplevels == 1, which this patch continues to enforce.

Reviewed-by: Lina Versace <lina@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33668>
2025-02-28 19:04:33 +00:00
Valentine Burley
7a3cfb57e5 anv/ci: Append -vk suffix to VKCTS job names
This aligns the naming with VKCTS jobs for other vendors and makes the
purpose of these jobs more explicit.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33793>
2025-02-28 09:26:29 +00:00
Guilherme Gallo
11f8dffec4 ci/angle: remove USE_ANGLE variable
Now that every ANGLE use is covered by tag consistency checks
(structured tagging), we don't need the USE_ANGLE flag anymore, because
if we have ANGLE_TAG set, it means that ANGLE is required in this job.

In detail, it means that the test job has inherited ANGLE_TAG from
`.container-builds-angle`.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33421>
2025-02-28 01:33:34 +00:00
Guilherme Gallo
3b01d6e900 ci/angle: test-time structured tag checks
Let's setup the CI to enable runner script to check if the ANGLE
binaries from the container/rootfs are matching the intended version.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33421>
2025-02-28 01:33:34 +00:00
Lionel Landwerlin
02341733df anv/iris: add drirc keys to disable VF/TE distribution
This is a request from debug engineers to be able to trace the HW
better when analyzing hangs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33795>
2025-02-27 21:10:59 +00:00
Lionel Landwerlin
bbade676f4 anv/iris: centralize TBIMR drirc
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33795>
2025-02-27 21:10:59 +00:00
Kevin Chuang
87ff7b061f anv/bvh: Fix copy shader handling sparse buffer
Fixes: 692b5fa9f2 ("anv: Add shader to copy acceleration structures")

This commit fixes the future test "sparse_binding_structures" for
"header_bottom_address" for ray tracing pipeline.

Even on 48-bit ray tracing (Xe1/2), the software-defined part
instance_leaf_part1.bvh_ptr has to be in canonical form for copy.comp
to deference a bvh, which means we have to preserve the upper 16bits.
This is especially relevant in cases where the acceleration structure buffer
is located high, such as sparse buffer.

Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33745>
2025-02-27 20:10:10 +00:00
Kevin Chuang
b9a980ea73 anv/bvh: Fix encoder handling sparse buffer
Fixes: 2fe57947e3 ("anv: Implement encode shader to fit in ANV BVH")

This commit resolves the failures in the future tests
"sparse_binding_structures" for rayquery. Sparse buffers' heaps are
located high, and since it's in canonical form, the higher 16bits are
all set to 1. However, the existing encoder did not expect any non-zero
values at the higher 16bits. As a result, the instance flags got
corrupted, causing most triangle tests to fail.

Thanks for Paulo providing insights about sparse buffer properties.

Co-developed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33745>
2025-02-27 20:10:10 +00:00