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anv: break down Wa_16014912113 in need/apply parts

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751>
This commit is contained in:
Lionel Landwerlin 2024-11-15 23:22:49 +02:00 • committed by Marge Bot
parent 93a327c4e6
commit 888b2ec7b0
5 changed files with 59 additions and 40 deletions
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17
src/intel/vulkan/anv_genX.h
View file

@ -137,6 +137,23 @@ genX(cmd_buffer_ensure_wa_14018283232)(struct anv_cmd_buffer *cmd_buffer,
}
#endif
static inline bool
genX(need_wa_16014912113)(const struct intel_urb_config *prev_urb_cfg,
const struct intel_urb_config *next_urb_cfg)
{
#if INTEL_NEEDS_WA_16014912113
/* When the config change and there was at a previous config. */
return intel_urb_setup_changed(prev_urb_cfg, next_urb_cfg,
MESA_SHADER_TESS_EVAL) &&
prev_urb_cfg->size[0] != 0;
#else
return false;
#endif
}
void genX(batch_emit_wa_16014912113)(struct anv_batch *batch,
const struct intel_urb_config *urb_cfg);
static inline bool
genX(cmd_buffer_set_coarse_pixel_active)(struct anv_cmd_buffer *cmd_buffer,
enum anv_coarse_pixel_state state)

5
src/intel/vulkan/genX_blorp_exec.c
View file

@ -267,7 +267,10 @@ blorp_pre_emit_urb_config(struct blorp_batch *blorp_batch,
struct intel_urb_config *urb_cfg)
{
struct anv_cmd_buffer *cmd_buffer = blorp_batch->driver_batch;
genX(urb_workaround)(cmd_buffer, urb_cfg);
if (genX(need_wa_16014912113)(&cmd_buffer->state.gfx.urb_cfg, urb_cfg)) {
genX(batch_emit_wa_16014912113)(&cmd_buffer->batch,
&cmd_buffer->state.gfx.urb_cfg);
}
/* Update urb config. */
memcpy(&cmd_buffer->state.gfx.urb_cfg, urb_cfg,

35
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -6365,41 +6365,6 @@ genX(batch_emit_fast_color_dummy_blit)(struct anv_batch *batch,
#endif
}
void
genX(urb_workaround)(struct anv_cmd_buffer *cmd_buffer,
const struct intel_urb_config *urb_cfg)
{
#if INTEL_NEEDS_WA_16014912113
const struct intel_urb_config *current =
&cmd_buffer->state.gfx.urb_cfg;
if (intel_urb_setup_changed(urb_cfg, current, MESA_SHADER_TESS_EVAL) &&
current->size[0] != 0) {
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBEntryAllocationSize = current->size[i] - 1;
urb.VSURBStartingAddressSlice0 = current->start[i];
urb.VSURBStartingAddressSliceN = current->start[i];
urb.VSNumberofURBEntriesSlice0 = i == 0 ? 256 : 0;
urb.VSNumberofURBEntriesSliceN = i == 0 ? 256 : 0;
}
#else
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBStartingAddress = current->start[i];
urb.VSURBEntryAllocationSize = current->size[i] - 1;
urb.VSNumberofURBEntries = i == 0 ? 256 : 0;
}
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.HDCPipelineFlushEnable = true;
}
}
#endif
}
struct anv_state
genX(cmd_buffer_begin_companion_rcs_syncpoint)(
struct anv_cmd_buffer *cmd_buffer)

39
src/intel/vulkan/genX_gfx_state.c
View file

@ -138,6 +138,39 @@ static const uint32_t vk_to_intel_primitive_type[] = {
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
};
void
genX(batch_emit_wa_16014912113)(struct anv_batch *batch,
const struct intel_urb_config *urb_cfg)
{
#if INTEL_NEEDS_WA_16014912113
if (urb_cfg->size[0] == 0)
return;
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBEntryAllocationSize = urb_cfg->size[i] - 1;
urb.VSURBStartingAddressSlice0 = urb_cfg->start[i];
urb.VSURBStartingAddressSliceN = urb_cfg->start[i];
urb.VSNumberofURBEntriesSlice0 = i == 0 ? 256 : 0;
urb.VSNumberofURBEntriesSliceN = i == 0 ? 256 : 0;
}
#else
anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBStartingAddress = urb_cfg->start[i];
urb.VSURBEntryAllocationSize = urb_cfg->size[i] - 1;
urb.VSNumberofURBEntries = i == 0 ? 256 : 0;
}
#endif
}
anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.HDCPipelineFlushEnable = true;
}
#endif
}
static void
genX(streamout_prologue)(struct anv_cmd_buffer *cmd_buffer)
{
@ -2140,8 +2173,10 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
}
if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_URB)) {
genX(urb_workaround)(cmd_buffer, &pipeline->urb_cfg);
if (genX(need_wa_16014912113)(&gfx->urb_cfg, &pipeline->urb_cfg)) {
genX(batch_emit_wa_16014912113)(&cmd_buffer->batch,
&gfx->urb_cfg);
}
anv_batch_emit_pipeline_state(&cmd_buffer->batch, pipeline, final.urb);
memcpy(&gfx->urb_cfg, &pipeline->urb_cfg,

3
src/intel/vulkan/genX_pipeline.c
View file

@ -463,8 +463,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
&constrained);
#if INTEL_NEEDS_WA_16014912113
if (intel_urb_setup_changed(urb_cfg_in, urb_cfg_out,
MESA_SHADER_TESS_EVAL) && urb_cfg_in->size[0] != 0) {
if (genX(need_wa_16014912113)(urb_cfg_in, urb_cfg_out)) {
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {