brw: Add block pointer in brw_inst

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33815>

src/intel/compiler/brw_cfg.cpp

@@ -187,6 +187,14 @@ bblock_t::unlink_list(exec_list *list)
    }
 }
 
+static void
+append_inst(bblock_t *block, brw_inst *inst)
+{
+   assert(inst->block == NULL);
+   inst->block = block;
+   block->instructions.push_tail(inst);
+}
+
 cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
    s(s)
 {
@@ -216,14 +224,14 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
 
       switch (inst->opcode) {
       case SHADER_OPCODE_FLOW:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
          next = new_block();
          cur->add_successor(mem_ctx, next, bblock_link_logical);
          set_next_block(&cur, next, ip);
          break;
 
       case BRW_OPCODE_IF:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
 	 /* Push our information onto a stack so we can recover from
 	  * nested ifs.
@@ -244,7 +252,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
 	 break;
 
       case BRW_OPCODE_ELSE:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
          cur_else = cur;
 
@@ -270,7 +278,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
             set_next_block(&cur, cur_endif, ip - 1);
          }
 
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
          if (cur_else) {
             cur_else->add_successor(mem_ctx, cur_endif, bblock_link_logical);
@@ -310,7 +318,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
             set_next_block(&cur, cur_do, ip - 1);
          }
 
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
          /* Represent divergent execution of the loop as a pair of alternative
           * edges coming out of the DO instruction: For any physical iteration
@@ -345,7 +353,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
 	 break;
 
       case BRW_OPCODE_CONTINUE:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
          /* A conditional CONTINUE may start a region of divergent control
           * flow until the start of the next loop iteration (*not* until the
@@ -373,7 +381,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
 	 break;
 
       case BRW_OPCODE_BREAK:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
          /* A conditional BREAK instruction may start a region of divergent
           * control flow until the end of the loop if the condition is
@@ -399,7 +407,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
 	 break;
 
       case BRW_OPCODE_WHILE:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 
          assert(cur_do != NULL && cur_while != NULL);
 
@@ -426,7 +434,7 @@ cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
 	 break;
 
       default:
-         cur->instructions.push_tail(inst);
+         append_inst(cur, inst);
 	 break;
       }
    }
@@ -745,6 +753,10 @@ cfg_t::validate(const char *stage_abbrev)
 
       cfgv_assert(!block->instructions.is_empty());
 
+      foreach_inst_in_block(brw_inst, inst, block) {
+         cfgv_assert(block == inst->block);
+      }
+
       brw_inst *first_inst = block->start();
       if (first_inst->opcode == BRW_OPCODE_DO) {
          /* DO instructions both begin and end a block, so the DO instruction

src/intel/compiler/brw_inst.cpp

@@ -956,23 +956,6 @@ brw_inst::is_volatile() const
             opcode == SHADER_OPCODE_SEND_GATHER) && send_is_volatile);
 }
 
-#ifndef NDEBUG
-static bool
-inst_is_in_block(const bblock_t *block, const brw_inst *inst)
-{
-   const exec_node *n = inst;
-
-   /* Find the tail sentinel. If the tail sentinel is the sentinel from the
-    * list header in the bblock_t, then this instruction is in that basic
-    * block.
-    */
-   while (!n->is_tail_sentinel())
-      n = n->get_next();
-
-   return n == &block->instructions.tail_sentinel;
-}
-#endif
-
 static void
 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 {
@@ -990,20 +973,21 @@ brw_inst::insert_before(bblock_t *block, brw_inst *inst)
    assert(this != inst);
    assert(block->end_ip_delta == 0);
 
-   if (!this->is_tail_sentinel())
-      assert(inst_is_in_block(block, this) || !"Instruction not in block");
+   assert(!inst->block || inst->block == block);
 
    block->end_ip++;
 
    adjust_later_block_ips(block, 1);
 
    exec_node::insert_before(inst);
+
+   inst->block = block;
 }
 
 void
 brw_inst::remove(bblock_t *block, bool defer_later_block_ip_updates)
 {
-   assert(inst_is_in_block(block, this) || !"Instruction not in block");
+   assert(this->block == block);
 
    if (exec_list_is_singular(&block->instructions)) {
       this->opcode = BRW_OPCODE_NOP;
@@ -1032,6 +1016,7 @@ brw_inst::remove(bblock_t *block, bool defer_later_block_ip_updates)
    }
 
    exec_node::remove();
+   this->block = NULL;
 }
 
 enum brw_reg_type

src/intel/compiler/brw_inst.h

@@ -234,6 +234,8 @@ public:
    const char *annotation;
    /** @} */
 #endif
+
+   bblock_t *block;
 };
 
 /**

src/intel/compiler/brw_validate.cpp

@@ -275,11 +275,12 @@ brw_validate(const brw_shader &s)
 {
    const intel_device_info *devinfo = s.devinfo;
 
+   if (s.cfg)
+      s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage));
+
    if (s.phase <= BRW_SHADER_PHASE_AFTER_NIR)
       return;
 
-   s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage));
-
    foreach_block(block, s.cfg) {
       /* Track the last used address register. Usage of the address register
        * in the IR should be limited to within a block, otherwise we would