fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-12 16:30:31 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv/iris: centralize TBIMR drirc

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33795>
This commit is contained in:
Lionel Landwerlin 2025-02-27 11:07:19 +02:00 • committed by Marge Bot
parent af1b4f61b5
commit bbade676f4
3 changed files with 5 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/iris/driinfo_iris.h
View file

@ -12,8 +12,8 @@ DRI_CONF_SECTION_END
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_ADAPTIVE_SYNC(true)
DRI_CONFIG_INTEL_TBIMR(true)
DRI_CONF_OPT_E(bo_reuse, 1, 0, 1, "Buffer object reuse",)
DRI_CONF_OPT_B(intel_tbimr, true, "Enable TBIMR tiled rendering")
DRI_CONF_OPT_I(generated_indirect_threshold, 100, 0, INT32_MAX, "Generated indirect draw threshold")
DRI_CONF_SECTION_END

2
src/intel/vulkan/anv_instance.c
View file

@ -32,7 +32,7 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_ANV_QUERY_COPY_WITH_SHADER_THRESHOLD(6)
DRI_CONF_ANV_FORCE_INDIRECT_DESCRIPTORS(false)
DRI_CONF_SHADER_SPILLING_RATE(11)
DRI_CONF_OPT_B(intel_tbimr, true, "Enable TBIMR tiled rendering")
DRI_CONFIG_INTEL_TBIMR(true)
DRI_CONF_ANV_COMPRESSION_CONTROL_ENABLED(false)
DRI_CONF_ANV_FAKE_NONLOCAL_MEMORY(false)
DRI_CONF_OPT_E(intel_stack_id, 512, 256, 2048,

3
src/util/driconf.h
View file

@ -327,6 +327,9 @@
DRI_CONF_OPT_B(fake_sparse, def, \
"Advertise support for sparse binding of textures regardless of real support")
#define DRI_CONFIG_INTEL_TBIMR(def) \
DRI_CONF_OPT_B(intel_tbimr, def, "Enable TBIMR tiled rendering")
#define DRI_CONF_INTEL_ENABLE_WA_14018912822(def) \
DRI_CONF_OPT_B(intel_enable_wa_14018912822, def, \
"Intel workaround for using zero blend constants")