Commit graph

147698 commits

Author SHA1 Message Date
Pavel Ondračka
c3f51a5dcf r300: allow presubtract when both ADD sources are negative
Current code doesn't handle this, however it is easy to make it work
by moving the negate to the presubtract source. Minor win in shader-db,
mostly with Unigine shaders.

Shader-db RV530:
total instructions in shared programs: 136382 -> 136236 (-0.11%)
instructions in affected programs: 9911 -> 9765 (-1.47%)
total temps in shared programs: 18939 -> 18942 (0.02%)
temps in affected programs: 37 -> 40 (8.11%)

Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18289>
2022-09-08 06:53:53 +00:00
Gert Wollny
1d8627deed virgl: Add some formats that the CTS uses
Otherwise running the CTS emits lots of warnings about
these formats missing in the drivers format table.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18462>
2022-09-08 06:38:48 +00:00
Rob Clark
bbef3cb9d3 egl: Relax locking
Now that we have the rwlock TerminateLock protecting us against
eglTerminate() yanking the rug from under us, drop the BDL across
calls to driver (or at least the main ones that can potentially
block).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7039
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:38 -07:00
Rob Clark
5d99e8cc03 egl: Introduce rwlock to protect eglTerminate()
eglTerminate() must be serialized against all other EGL calls.  But in
most cases, other EGL calls do not need to be serialized against each
other.  Which fits rather well with a rwlock.

One would be tempted to simply replace the existing BDL with a rwlock,
but several portability and debuggability limitations of the rwlock
implementation prevent that, as described in the TerminateLock comment
block.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:34 -07:00
Rob Clark
7ba2784b0a egl: Make RefCount atomic
Once we relax the locking, we will be doing _eglPutFoo() outside of the
big display lock.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:29 -07:00
Rob Clark
f1efe037df egl/dri2: Add display lock
In preperation of relaxing eglapi to not hold a lock across driver
calls, but instead only for protecting it's own state, add our own
lock to protect code paths that need locking or have not been audited
yet.  The blocking calls (ClientWaitSyncKHR) or critical path and/or
blocking (MakeCurrent, SwapBuffers*) are lockless, as they have already
been audited for thread safety.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:25 -07:00
Rob Clark
fc5281286d egl/dri2: Make ref_count atomic
In particular, MakeCurrent can be called on multiple threads in
parallel.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:21 -07:00
Rob Clark
a2d6dee4f0 egl/wgl: Make ref_count atomic
Looks like wgl doesn't have much display state to protect.  But it's
ref_count should be atomic before we start removing locking from eglapi
to protect against MakeCurrent being called in parallel on multiple
threads.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:16 -07:00
Timothy Arceri
f182b1952a glsl: remove GLSL IR inverse comparison optimisations
As per 7d85dc4f35 GLSL IR is not smart enough to handle this
correctly for NANs.

Shader-db radeonsi (RX 6800):

Totals from affected shaders:
SGPRS: 26848 -> 26848 (0.00 %)
VGPRS: 13552 -> 13552 (0.00 %)
Spilled SGPRs: 134 -> 134 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 635000 -> 630988 (-0.63 %) bytes
Max Waves: 5474 -> 5474 (0.00 %)

Shader-db iris (BDW):

total instructions in shared programs: 17538859 -> 17539018 (<.01%)
instructions in affected programs: 29369 -> 29528 (0.54%)
helped: 3
HURT: 126
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.49% max: 0.49% x̄: 0.49% x̃: 0.49%
HURT stats (abs)   min: 1 max: 2 x̄: 1.29 x̃: 1
HURT stats (rel)   min: 0.27% max: 1.32% x̄: 0.61% x̃: 0.54%
95% mean confidence interval for instructions value: 1.13 1.33
95% mean confidence interval for instructions %-change: 0.54% 0.63%
Instructions are HURT.

total loops in shared programs: 4866 -> 4866 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cycles in shared programs: 858548230 -> 858548915 (<.01%)
cycles in affected programs: 1331737 -> 1332422 (0.05%)
helped: 0
HURT: 92
HURT stats (abs)   min: 2 max: 49 x̄: 7.45 x̃: 6
HURT stats (rel)   min: 0.01% max: 1.90% x̄: 0.12% x̃: 0.05%
95% mean confidence interval for cycles value: 5.72 9.17
95% mean confidence interval for cycles %-change: 0.05% 0.19%
Cycles are HURT.

Note: With the addition of "nir/comparison_pre: See through an inot to
apply the optimization", idr's shader-db results are:

All Broadwell and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19940805 -> 19940802 (<.01%)
instructions in affected programs: 582 -> 579 (-0.52%)
helped: 3 / HURT: 0

total cycles in shared programs: 858431633 -> 858431747 (<.01%)
cycles in affected programs: 4938 -> 5052 (2.31%)
helped: 0 / HURT: 3

All older Intel platforms had similar results. (Haswell shown)
total instructions in shared programs: 16715626 -> 16715670 (<.01%)
instructions in affected programs: 9496 -> 9540 (0.46%)
helped: 0 / HURT: 44

total cycles in shared programs: 881224396 -> 881232314 (<.01%)
cycles in affected programs: 600610 -> 608528 (1.32%)
helped: 6 / HURT: 44

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Ian Romanick
5473536798 nir/comparison_pre: See through an inot to apply the optimization
This also prevents some small regressions in "glsl: remove GLSL IR
inverse comparison optimisations".

shader-db results:

All Sandy Bridge and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19941025 -> 19940805 (<.01%)
instructions in affected programs: 52431 -> 52211 (-0.42%)
helped: 188 / HURT: 6

total cycles in shared programs: 858451784 -> 858431633 (<.01%)
cycles in affected programs: 2119134 -> 2098983 (-0.95%)
helped: 183 / HURT: 12

LOST:   2
GAINED: 0

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8364668 -> 8364670 (<.01%)
instructions in affected programs: 753 -> 755 (0.27%)
helped: 2 / HURT: 4

total cycles in shared programs: 248752572 -> 248752238 (<.01%)
cycles in affected programs: 87290 -> 86956 (-0.38%)
helped: 2 / HURT: 4

fossil-db results:

Skylake, Ice Lake, and Tiger Lake had similar results. (Ice Lake shown)
Instructions in all programs: 144909184 -> 144909130 (-0.0%)
Instructions helped: 6

Cycles in all programs: 9138641740 -> 9138640984 (-0.0%)
Cycles helped: 8

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Timothy Arceri
61c3438b27 nir: support loop unrolling with inot conditions
Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.

This change avoids 292 loop unrolling regressions with shader-db
once the following patch is applied.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Timothy Arceri
96c19d23c9 nir: update nir_is_supported_terminator_condition()
Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.

Here we simply check to see if the inot contains a simple
terminator condition we previously handled. We also update
the previous users of this function to use a newly name
copy of the previous behaviour
nir_is_terminator_condition_with_two_inputs().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Bas Nieuwenhuizen
ae7532e0cc amd/common: Disable DCC retile modifiers on RDNA1
Some claims of corruption, modifier-less Mesa already doesn't do
it. Since these modifiers have no purpose besides being displayed
lets just disable in Mesa.

Cc: mesa-stable

Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140>
2022-09-07 23:41:28 +00:00
Bas Nieuwenhuizen
af4b656817 amd/common: Don't rely on DCN support checks with modifiers.
Going to be a bad time if they disagree, which is bound to happen
sometimes. Not asserting and stuff tends to be a better experience
than crashing.

Cc: mesa-stable

Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140>
2022-09-07 23:41:28 +00:00
Yiwei Zhang
4ae4e4362c venus: double the abort timeout
To avoid bumping abort timeout too much. This change also doubles the
busy wait cycles, which would further reduce unnecessary sleeps for
synchronous calls. Ultimately, after we fix the fencing and push all
roundtrip waiting to the renderer side as well as we fixing the abort
logic, we can live with busy wait alone here.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18472>
2022-09-07 18:48:07 +00:00
Iván Briano
92ee2e6b64 anv: pipelineStageCreationFeedbackCount is allowed to be 0
Fixes: 6601e5d6fc ("anv: implement VK_EXT_pipeline_creation_feedback")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18451>
2022-09-07 10:49:29 -07:00
Georg Lehmann
28a69b72d8 aco: Use plain VOPC for vcmpx when possible.
Foz-DB Navi21:
Totals from 66947 (49.62% of 134913) affected shaders:
CodeSize: 210383024 -> 210033376 (-0.17%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18417>
2022-09-07 16:08:36 +00:00
Konstantin Seurer
9cbc609db3 radv: Deduplicate push constant structs
This patch adds a header that is shared between the accel struct build
kernels and the dispatch code.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18376>
2022-09-07 15:45:48 +00:00
Mike Blumenkrantz
69d123d88e zink: fix sharedmem ops with bit_size!=32
* the rewrite_bo_access compiler pass already handles 64bit rewrites as-needed
* sharedmem access is not required to be 32bit

thus, this can use a similar methodology as ssbo/ubo vars to index based on bitsize
and handle operations through sized variables

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18449>
2022-09-07 15:23:03 +00:00
Eric Engestrom
28ed514c3c v3dv: implement VK_EXT_shader_module_identifier
Passes `dEQP-VK.*.shader_module_identifier.*`

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18458>
2022-09-07 12:51:16 +00:00
Tomeu Vizoso
0704926a9c Revert "Revert "Revert "ci: set venus on lavapipe to manual due to flakes"""
Now the flakiness might have been fixed for good.

This reverts commit e51c5a18ad.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18454>
2022-09-07 09:18:49 +00:00
Samuel Pitoiset
d6321fee5f radv: only expose sparseResidencyImage3D on GFX9+
It's currently broken on Polaris10 and breaks running VKCTS entirely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18457>
2022-09-07 08:57:13 +00:00
Martin Roukala (né Peres)
daafeb9893 radv/ci: run vkcts on the two steam decks in parallel
We just added a new Steam Deck to our CI, which should allow us to
halve the execution time of a full VKCTS run from 1h20 to a more
reasonable 40 minutes.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18432>
2022-09-07 08:37:59 +00:00
Samuel Pitoiset
8fcb4aa0eb radv: compact MRTs to save PS export memory space
If there are holes between color outputs (e.g. a shader exports MRT1,
but not MRT0), we can remove the holes by moving higher MRTs lower. The
hardware will remap the MRTs to their correct locations if we remove
holes in SPI_SHADER_COL_FORMAT but not CB_SHADER_MASK. This is good for
performance because the hardware will allocate less space for color
MRTs.

This also allows to remove even more unused color exports because we no
longer need to force previous targets to be non-zero. Only SotTR seems
affected from our fossils db.

fossils-db (NAVI21):
Totals from 859 (0.64% of 134913) affected shaders:
VGPRs: 24328 -> 24216 (-0.46%)
CodeSize: 1433276 -> 1422576 (-0.75%)
Instrs: 255275 -> 253728 (-0.61%)
Latency: 1666836 -> 1661544 (-0.32%)
InvThroughput: 346038 -> 343406 (-0.76%)
Copies: 16520 -> 16506 (-0.08%)
PreSGPRs: 25934 -> 25920 (-0.05%)
PreVGPRs: 19903 -> 19662 (-1.21%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5786>
2022-09-07 08:17:20 +00:00
Samuel Pitoiset
49c7d28b0b radv: gather MRTs that are written by the fragment shader
This will be used to filter color attachments without exports.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5786>
2022-09-07 08:17:20 +00:00
Erik Faye-Lund
00c4882bc9 vc4: do not attempt to do deep tiled blits
We only copy a single layer, so let's not even try to support deep
blits here.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18427>
2022-09-07 07:50:44 +00:00
Erik Faye-Lund
eb2307ec69 vc4: respect z-offset in tiled blits
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18427>
2022-09-07 07:50:44 +00:00
Erik Faye-Lund
c3e1c16b96 v3d: do not pretend to fake rgtc-support
The is_format_support query doesn't pretent to have RGTC support, so
this doesn't seem like it ever did anything useful.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18439>
2022-09-07 07:31:00 +00:00
Tapani Pälli
d276ad4520 intel/compiler: implement Wa_14014595444 for DG2
According to the workaround, we should setup MLOD as parameter
4 and 5 for the sample_b message.

v2: only SAMPLE_B, not SAMPLE_B_C (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18408>
2022-09-07 05:44:56 +00:00
Tapani Pälli
f32ac1d30b anv: implement Wa_14015946265 for DG2
SOL unit issues, wa is to send PC with CS stall after SO_DECL.

v2: emit also in genX_gpu_memcpy (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18409>
2022-09-07 04:38:05 +00:00
Tapani Pälli
e37f534d7f iris: implement Wa_14015946265 for DG2
SOL unit issues, wa is to send PC with CS stall after SO_DECL.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18409>
2022-09-07 04:38:05 +00:00
Bas Nieuwenhuizen
6e020dff99 radv: Expose 3d sparse images.
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18165>
2022-09-06 23:16:26 +00:00
Bas Nieuwenhuizen
c738c99a4a radv: Add 3d tile shapes for sparse binding.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18165>
2022-09-06 23:16:26 +00:00
Bas Nieuwenhuizen
5a2efa98d9 radv: Add binding code for 3d sparse images.
GFX7-8 code is kinda expected. For GFX9 and GFX10 the entire
mipchain is duplicated by "layer" even though smaller mips also
have less layers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18165>
2022-09-06 23:16:26 +00:00
Alyssa Rosenzweig
08c612b5ce asahi: Allocate new cmdbufs if out of space
Instead of crashing when we run out of space in the command buffer,
allocate a new buffer, jump to it with the STREAM_LINK command, and
use it to write new commands.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:29 +00:00
Alyssa Rosenzweig
a7ddb8ebf7 asahi: Handle Stream Link VDM commands
Jumps in the command streams, allowing us to chain ("link") command
buffers. Naming is from PowerVR, which contains an identical command.
PowerVR's has conditional jumps and function call support, it's likely
that AGX inherited this too but I haven't tested that. (Those might be
useful for conditional rendering and secondary command buffers
respectively?)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
6f5c8d0e24 asahi: Express VDM commands according to PowerVR
Piles of unknown bits go away, as we find they're either "field present"
bits or block types. And yep, the block type enum lines up between AGX
and RGX.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
80d8273705 asahi: Annotate VDM/CDM commands as per PVR
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
1a460d1c7e asahi: Make BO list growable
Back it by a simple dynamic array, ralloc'd off the batch (and make the
context/batch ralloc'd so stuff gets cleaned up).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
22f6efde02 asahi: Dirty track everything
Now that we have fine grained state emit code, let's use it to reduce
driver overhead. Dirty tracking is delicate: while this seems to work,
I've also added an ASAHI_MESA_DEBUG=dirty option in debug builds
to disable the optimizations here for future debug.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
44853b4d01 asahi: Hoist constant PPP state to start of batch
This reduces how much we emit per draw.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
942bda7f2d asahi: Match PPP data structures with PowerVR
Looking at PowerVR's PPP definitions in tree in Mesa
(src/imagination/csbgen/), we find that AGX's "tagged" data structures
are actually sequences of state items prefixed by a header specifying
which state follows. Rather than hardcoding the sequences in which Apple's
driver chooses to bundle state, we need the XML to be flexible enough to
encode or decode any valid combination of state. That means reworking
the XML. While doing so, we find a number of fields that are identical
between RGX and AGX, and fix the names while at it (for example, the W
Clamp floating point).

Names are from the PowerVR code in Mesa where sensible.

Once we've reworked the XML, we need to rework the decoder.  Instead of
reading tags and printing the combined state packets, the decoder now
must unpack the header and print the individual state items specified by
the header, with slightly more complicated bounds checking.

Finally, state emission in the driver becomes much more flexible. To
prove the flexibility actually works, we now emit all PPP state (except for
viewport and scissor state) as a single PPP update. This works. After
this we can move onto more interesting arrangements of state for lower
driver overhead.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
baadc1ec13 asahi: Don't use lower_wpos_pntc
Instead we can flip point coords with the object type. That means fewer
instructions without shader variants. Thanks, PowerVR ^_^

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
f7ef5eefdd asahi: Identify object type field via PowerVR
src/imagination/csbgen/rogue_ppp.xml STATE_ISPA bits 28. Looks like that
got split into two structs in AGX (with info duplicated?) but yeah I
have a lot to work with here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig
d93878f77a asahi: Split RASTERIZER into constituent words
As done in the PowerVR driver.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Yiwei Zhang
d399685da5 venus: enable KHR_driver_properties on Android
Venus has a driver id now and Android cts has been patched.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18447>
2022-09-06 19:52:26 +00:00
Yiwei Zhang
61e899a181 venus: enable zink required extensions on Android
Below extensions are enabled:
- VK_KHR_external_memory_fd
- VK_EXT_external_memory_dma_buf
- VK_EXT_image_drm_format_modifier

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18447>
2022-09-06 19:52:26 +00:00
Yiwei Zhang
ac95ecd044 venus: some clang format fixes
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18447>
2022-09-06 19:52:26 +00:00
Lionel Landwerlin
492761ab8d anv: add a new NO_LOCAL_MEM allocation flag
We found a perf regression with 9027c5df4c ("anv: remove the
LOCAL_MEM allocation bit") which seems to be that we over subscribe
local memory, leading i915 to swap things in/out too much.

This change avoid putting buffers in local memory if they are not
allocated from a DEVICE_LOCAL heap.

Maybe we can revisit this later if i915 is better able to deal with
more buffers in local memory.

v2: Remove implicit_css from anv_bo when not in lmem (Ivan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9027c5df4c ("anv: remove the LOCAL_MEM allocation bit")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7188
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18395>
2022-09-06 18:24:00 +00:00
Adam Jackson
f41a6504a1 egl/kopper: Don't add EGL_SWAP_BEHAVIOR_PRESERVED_BIT configs
It's strictly inferior to EGL_EXT_buffer_age so apps shouldn't bother to
begin with, and we don't communicate the surface preservation state to
the backend so we don't handle it correctly in any case.

Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18214>
2022-09-06 17:46:50 +00:00