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Author SHA1 Message Date
Marek Olšák
45a71d5de5 radeonsi: handle incompatible DCC formats in resource_copy_region 
Required because of later commits.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
 2017-03-30 16:09:39 +02:00
Marek Olšák
b05b8587ae radeonsi: remove a workaround for inexact *8_SNORM blits 
All tests pass on Fiji now. This prevents DCC disablement due to
incompatible DCC formats due to the fallback.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
 2017-03-30 16:09:39 +02:00
Marek Olšák
a955ee788f gallium/radeon: add and use a new helper vi_dcc_enabled 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2017-03-30 16:09:37 +02:00
Marek Olšák
f7bd51626e gallium/radeon: formalize that r600_query_hw_add_result doesn't need a context 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2017-03-30 16:09:36 +02:00
Marek Olšák
d76c306162 radeonsi: don't make a copy of pipe_index_buffer in draw_vbo 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2017-03-30 16:09:32 +02:00
Marek Olšák
abb25fb18e gallium/util: use const in u_index_modify helpers 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2017-03-30 16:09:29 +02:00
Samuel Pitoiset
7d99f48b5e winsys/amdgpu: remove AMDGPU_INFO_NUM_EVICTIONS 
This is now exposed with libdrm_amdgpu 2.4.76.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 15:27:13 +02:00
Marek Olšák
675af982e1 radeonsi: add Vega10 PCI IDs 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Boyuan Zhang
cb8b84e3d0 radeon/uvd: set correct vega10 db pitch alignment 
Create new function to get correct alignment based on Asics, and change
the corresponding decode message buffer and dpb buffer size calculations

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2017-03-30 14:44:33 +02:00
Leo Liu
5eba761fee radeon/vce: add vce support for firmware 53.19.4 
v2: squashed with other similar commits

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2017-03-30 14:44:33 +02:00
Leo Liu
ed48b399f1 radeon/vce: adapt gfx9 surface to vce 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2017-03-30 14:44:33 +02:00
Leo Liu
6c7870fee8 winsys/surface: add height pitch for gfx9 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
 2017-03-30 14:44:33 +02:00
Leo Liu
c89e771c9c radeon/uvd: clear message buffer when reuse 
As required by firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2017-03-30 14:44:33 +02:00
Leo Liu
c836f2ce28 radeon/uvd: adapt gfx9 surface to uvd 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2017-03-30 14:44:33 +02:00
Leo Liu
9d5db4e8f4 radeon/uvd: add uvd soc15 register 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
474468fbf9 radeonsi/gfx9: disable features that don't work 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
8ea3da0706 radeonsi/gfx9: only allow GL 3.1 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
7695ea0c02 radeonsi/gfx9: add linear address computations for texture transfers 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
172b05a37e radeonsi/gfx9: don't generate LS and ES states 
these shaders don't exist on GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
eb22f5bf6f radeonsi/gfx9: SPI_SHADER_USER_DATA changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
f4ab7a5415 winsys/amdgpu: set/get BO tiling flags for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
7d88233f84 radeonsi/gfx9: handle pitch and offset overrides for texture_from_handle 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
de55e57e29 radeonsi/gfx9: set/validate GFX9 BO metadata 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
bd1da6b339 radeonsi/gfx9: add radeon_surf.gfx9.surf_offset 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
3685a12bad radeonsi/gfx9: don't write mipmap level offsets to BO metadata 
GFX9 doesn't have (usable) mipmap offsets.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
9c100bd693 radeonsi/gfx9: flush CB & DB caches with an EOP TS event 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
6e0d64712a radeonsi/gfx9: use ACQUIRE_MEM 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
81aa21d732 radeonsi/gfx9: only use CE RAM for most-used descriptors 
because the CE RAM size decreased to 4 KB.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
86f13c7363 radeonsi/gfx9: emit FLUSH_DFSM where required 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
ad93d72c34 radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_state 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
405bacd820 radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
354285afa0 radeonsi/gfx9: fix textureSize/imageSize for 1D textures 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
566defad13 radeonsi/gfx9: add a workaround for 1D depth textures 
The same workaround is used by Vulkan.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
fc3c503b5d radeonsi/gfx9: enable clamping for Z UNORM formats promoted to Z32F 
so that shaders don't have to do it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
5abf60076c radeonsi/gfx9: image descriptor changes in mutable fields 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
c8ffec4f4b radeonsi/gfx9: FMASK image descriptor changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
d60f72a9f0 radeonsi/gfx9: image descriptor changes in immutable fields 
The border color swizzle logic was copied from Vulkan. It doesn't make any
sense to me, but it passes all piglits except the stencil ones.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
dfd2b54948 radeonsi/gfx9: DB changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
94819a3e6c radeonsi/gfx9: CB changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
272b50a6f4 radeonsi/gfx9: do DCC clears on non-mipmapped textures only 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
aba8e0ea68 radeonsi/gfx9: update can_sample_z/s flags 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
054dcbe42c radeonsi/gfx9: pass correct parameters to buffer_get_handle 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
710aaed52b radeonsi/gfx9: update si_set_optimal_micro_tile_mode 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
7fcad40ca5 radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE 
GFX9 supports this with all modes except linear.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
6f09b0d076 radeonsi/gfx9: update HTILE/CMASK/FMASK allocators 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
281542c690 radeonsi/gfx9: stub testdma - array_mode_to_string 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
a0e8b73594 radeonsi/gfx9: update r600_print_texture_info 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
b25d7c2cbf gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.* 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
9b365d497a winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
493de7f935 winsys/amdgpu: wire up new addrlib for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00