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radeonsi/gfx9: disable features that don't work

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-03-14 23:26:30 +01:00
parent 8ea3da0706
commit 474468fbf9
4 changed files with 15 additions and 5 deletions
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8
src/gallium/drivers/radeon/r600_texture.c
View file

@ -1625,7 +1625,9 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
* Use the staging texture for uploads if the underlying BO
* is busy.
*/
if (!rtex->surface.is_linear)
/* TODO: Linear CPU mipmap addressing is broken on GFX9: */
if (!rtex->surface.is_linear ||
(rctx->chip_class == GFX9 && level))
use_staging_texture = true;
else if (usage & PIPE_TRANSFER_READ)
use_staging_texture =
@ -2632,6 +2634,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
if (rctx->render_cond)
return;
/* TODO: fix CMASK and DCC fast clear */
if (rctx->chip_class >= GFX9)
return;
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;

5
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -4590,8 +4590,9 @@ static void tex_fetch_args(
* The sample index should be adjusted as follows:
* sample_index = (fmask >> (sample_index * 4)) & 0xF;
*/
if (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
if (ctx->screen->b.chip_class <= VI && /* TODO: fix FMASK on GFX9 */
(target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
struct lp_build_context *uint_bld = &bld_base->uint_bld;
struct lp_build_emit_data txf_emit_data = *emit_data;
LLVMValueRef txf_address[4];

4
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
View file

@ -834,7 +834,9 @@ static void emit_declaration(struct lp_build_tgsi_context *bld_base,
*
* LLVM 3.8 crashes with this.
*/
if (HAVE_LLVM >= 0x0309 && array_size > 16) {
if ((HAVE_LLVM >= 0x0309 && array_size > 16) ||
/* TODO: VGPR indexing is buggy on GFX9. */
ctx->screen->b.chip_class == GFX9) {
array_alloca = LLVMBuildAlloca(builder,
LLVMArrayType(bld_base->base.vec_type,
array_size), "array");

3
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2198,7 +2198,8 @@ static void si_initialize_color_surface(struct si_context *sctx,
S_028C74_NUM_FRAGMENTS(log_samples);
if (rtex->fmask.size) {
color_info |= S_028C70_COMPRESSION(1);
/* TODO: fix FMASK on GFX9: */
color_info |= S_028C70_COMPRESSION(sctx->b.chip_class <= VI);
unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
if (sctx->b.chip_class == SI) {