mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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radeonsi/gfx9: DB changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
94819a3e6c
commit
dfd2b54948
2 changed files with 171 additions and 89 deletions
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@ -307,17 +307,19 @@ struct r600_surface {
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struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
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/* DB registers. */
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uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
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uint64_t db_stencil_base; /* EG and later */
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uint64_t db_htile_data_base;
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unsigned db_depth_info; /* R600 only, then SI and later */
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unsigned db_z_info; /* EG and later */
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unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
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unsigned db_z_info2; /* GFX9+ */
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unsigned db_depth_view;
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unsigned db_depth_size;
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unsigned db_depth_slice; /* EG and later */
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unsigned db_stencil_base; /* EG and later */
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unsigned db_stencil_info; /* EG and later */
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unsigned db_stencil_info2; /* GFX9+ */
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unsigned db_prefetch_limit; /* R600 only */
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unsigned db_htile_surface;
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unsigned db_htile_data_base;
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unsigned db_preload_control; /* EG and later */
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};
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@ -2244,7 +2244,6 @@ static void si_init_depth_surface(struct si_context *sctx,
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{
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struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
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unsigned level = surf->base.u.tex.level;
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struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
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unsigned format, stencil_format;
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uint32_t z_info, s_info;
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@ -2261,87 +2260,140 @@ static void si_init_depth_surface(struct si_context *sctx,
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surf->db_htile_data_base = 0;
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surf->db_htile_surface = 0;
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assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
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if (sctx->b.chip_class >= GFX9) {
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surf->db_depth_base = rtex->resource.gpu_address >> 8;
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surf->db_stencil_base = (rtex->resource.gpu_address +
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rtex->surface.u.gfx9.stencil_offset) >> 8;
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z_info = S_028038_FORMAT(format) |
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S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
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S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
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S_028038_MAXMIP(rtex->resource.b.b.last_level);
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s_info = S_02803C_FORMAT(stencil_format) |
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S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
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surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
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surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
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surf->db_depth_view |= S_028008_MIPID(level);
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surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
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S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
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surf->db_depth_base = (rtex->resource.gpu_address +
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rtex->surface.u.legacy.level[level].offset) >> 8;
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surf->db_stencil_base = (rtex->resource.gpu_address +
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rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
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/* Only use HTILE for the first level. */
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if (rtex->htile_buffer && !level) {
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z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
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S_028038_ALLOW_EXPCLEAR(1);
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z_info = S_028040_FORMAT(format) |
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S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
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s_info = S_028044_FORMAT(stencil_format);
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surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
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if (rtex->tc_compatible_htile) {
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unsigned max_zplanes = 4;
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if (sctx->b.chip_class >= CIK) {
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struct radeon_info *info = &sctx->screen->b.info;
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unsigned index = rtex->surface.u.legacy.tiling_index[level];
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unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
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unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
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unsigned tile_mode = info->si_tile_mode_array[index];
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unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
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unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
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if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
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rtex->resource.b.b.nr_samples > 1)
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max_zplanes = 2;
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surf->db_depth_info |=
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S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
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S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
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S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
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S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
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S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
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S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
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z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
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s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
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z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
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S_028038_ITERATE_FLUSH(1);
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s_info |= S_02803C_ITERATE_FLUSH(1);
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}
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if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
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/* Stencil buffer workaround ported from the SI-CI-VI code.
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* See that for explanation.
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*/
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s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
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} else {
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/* Use all HTILE for depth if there's no stencil. */
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s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
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}
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surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
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surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
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S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
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S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
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}
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} else {
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unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
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z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
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tile_mode_index = si_tile_mode_index(rtex, level, true);
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s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
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}
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/* SI-CI-VI */
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struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
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surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
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S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
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surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
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levelinfo->nblk_y) / 64 - 1);
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assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
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/* Only use HTILE for the first level. */
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if (rtex->htile_buffer && !level) {
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z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
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S_028040_ALLOW_EXPCLEAR(1);
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surf->db_depth_base = (rtex->resource.gpu_address +
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rtex->surface.u.legacy.level[level].offset) >> 8;
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surf->db_stencil_base = (rtex->resource.gpu_address +
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rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
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if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
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/* Workaround: For a not yet understood reason, the
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* combination of MSAA, fast stencil clear and stencil
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* decompress messes with subsequent stencil buffer
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* uses. Problem was reproduced on Verde, Bonaire,
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* Tonga, and Carrizo.
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*
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* Disabling EXPCLEAR works around the problem.
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*
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* Check piglit's arb_texture_multisample-stencil-clear
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* test if you want to try changing this.
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*/
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if (rtex->resource.b.b.nr_samples <= 1)
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s_info |= S_028044_ALLOW_EXPCLEAR(1);
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} else if (!rtex->tc_compatible_htile) {
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/* Use all of the htile_buffer for depth if there's no stencil.
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* This must not be set when TC-compatible HTILE is enabled
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* due to a hw bug.
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*/
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s_info |= S_028044_TILE_STENCIL_DISABLE(1);
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z_info = S_028040_FORMAT(format) |
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S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
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s_info = S_028044_FORMAT(stencil_format);
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surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
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if (sctx->b.chip_class >= CIK) {
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struct radeon_info *info = &sctx->screen->b.info;
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unsigned index = rtex->surface.u.legacy.tiling_index[level];
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unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
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unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
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unsigned tile_mode = info->si_tile_mode_array[index];
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unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
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unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
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surf->db_depth_info |=
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S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
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S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
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S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
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S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
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S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
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S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
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z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
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s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
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} else {
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unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
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z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
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tile_mode_index = si_tile_mode_index(rtex, level, true);
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s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
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}
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surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
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surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
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surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
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S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
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surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
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levelinfo->nblk_y) / 64 - 1);
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if (rtex->tc_compatible_htile) {
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surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
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/* Only use HTILE for the first level. */
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if (rtex->htile_buffer && !level) {
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z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
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S_028040_ALLOW_EXPCLEAR(1);
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if (rtex->resource.b.b.nr_samples <= 1)
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z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
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else if (rtex->resource.b.b.nr_samples <= 4)
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z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
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else
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z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
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if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
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/* Workaround: For a not yet understood reason, the
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* combination of MSAA, fast stencil clear and stencil
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* decompress messes with subsequent stencil buffer
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* uses. Problem was reproduced on Verde, Bonaire,
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* Tonga, and Carrizo.
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*
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* Disabling EXPCLEAR works around the problem.
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*
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* Check piglit's arb_texture_multisample-stencil-clear
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* test if you want to try changing this.
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*/
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if (rtex->resource.b.b.nr_samples <= 1)
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s_info |= S_028044_ALLOW_EXPCLEAR(1);
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} else if (!rtex->tc_compatible_htile) {
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/* Use all of the htile_buffer for depth if there's no stencil.
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* This must not be set when TC-compatible HTILE is enabled
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* due to a hw bug.
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*/
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s_info |= S_028044_TILE_STENCIL_DISABLE(1);
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}
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surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
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surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
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if (rtex->tc_compatible_htile) {
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surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
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if (rtex->resource.b.b.nr_samples <= 1)
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z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
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else if (rtex->resource.b.b.nr_samples <= 4)
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z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
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else
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z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
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}
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}
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}
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@ -2694,30 +2746,58 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
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RADEON_PRIO_HTILE);
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}
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radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
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radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
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if (sctx->b.chip_class >= GFX9) {
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radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
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radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
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radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
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radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
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radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
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radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
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radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
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S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
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radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
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radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
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radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
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radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
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radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
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radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
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radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
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radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
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radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
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S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
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radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
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radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
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radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
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radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
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radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
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radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
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radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
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radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
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radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
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radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
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radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
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radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
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} else {
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radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
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radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
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radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
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radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
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S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
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radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
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radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
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radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
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radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
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radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
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radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
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radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
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}
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radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
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radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
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radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
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radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
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radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
|
||||
} else if (sctx->framebuffer.dirty_zsbuf) {
|
||||
radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
|
||||
radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
|
||||
radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
|
||||
if (sctx->b.chip_class >= GFX9)
|
||||
radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
|
||||
else
|
||||
radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
|
||||
|
||||
radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
|
||||
radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
|
||||
}
|
||||
|
||||
/* Framebuffer dimensions. */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue