mirror of
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winsys/amdgpu: wire up new addrlib for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
e572835fea
commit
493de7f935
1 changed files with 399 additions and 1 deletions
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@ -585,10 +585,408 @@ static int gfx6_surface_init(struct radeon_winsys *rws,
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return 0;
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}
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/* This is only called when expecting a tiled layout. */
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static int
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gfx9_get_preferred_swizzle_mode(struct amdgpu_winsys *ws,
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ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
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bool is_fmask, AddrSwizzleMode *swizzle_mode)
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{
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ADDR_E_RETURNCODE ret;
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ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
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ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
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sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
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sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
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sin.flags = in->flags;
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sin.resourceType = in->resourceType;
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sin.format = in->format;
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sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
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/* TODO: We could allow some of these: */
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sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
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sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
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sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
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sin.bpp = in->bpp;
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sin.width = in->width;
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sin.height = in->height;
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sin.numSlices = in->numSlices;
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sin.numMipLevels = in->numMipLevels;
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sin.numSamples = in->numSamples;
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sin.numFrags = in->numFrags;
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if (is_fmask) {
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sin.flags.color = 0;
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sin.flags.fmask = 1;
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}
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ret = Addr2GetPreferredSurfaceSetting(ws->addrlib, &sin, &sout);
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if (ret != ADDR_OK)
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return ret;
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*swizzle_mode = sout.swizzleMode;
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return 0;
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}
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static int gfx9_compute_miptree(struct amdgpu_winsys *ws,
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struct radeon_surf *surf, bool compressed,
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ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
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{
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ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
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ADDR_E_RETURNCODE ret;
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out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
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out.pMipInfo = mip_info;
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ret = Addr2ComputeSurfaceInfo(ws->addrlib, in, &out);
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if (ret != ADDR_OK)
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return ret;
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if (in->flags.stencil) {
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surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
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surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
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out.mipChainPitch - 1;
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surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
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surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
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surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
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return 0;
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}
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surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
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surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
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out.mipChainPitch - 1;
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surf->u.gfx9.surf_slice_size = out.sliceSize;
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surf->u.gfx9.surf_pitch = out.pitch;
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surf->surf_size = out.surfSize;
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surf->surf_alignment = out.baseAlign;
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if (in->swizzleMode == ADDR_SW_LINEAR) {
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for (unsigned i = 0; i < in->numMipLevels; i++)
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surf->u.gfx9.surf_ymip_offset[i] = mip_info[i].mipOffsetYPixel;
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}
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if (in->flags.depth) {
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assert(in->swizzleMode != ADDR_SW_LINEAR);
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/* HTILE */
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ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
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ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
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hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
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hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
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hin.hTileFlags.pipeAligned = 1;
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hin.hTileFlags.rbAligned = 1;
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hin.depthFlags = in->flags;
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hin.swizzleMode = in->swizzleMode;
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hin.unalignedWidth = in->width;
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hin.unalignedHeight = in->height;
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hin.numSlices = in->numSlices;
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hin.numMipLevels = in->numMipLevels;
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ret = Addr2ComputeHtileInfo(ws->addrlib, &hin, &hout);
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if (ret != ADDR_OK)
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return ret;
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surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
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surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
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surf->htile_size = hout.htileBytes;
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surf->htile_alignment = hout.baseAlign;
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} else {
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/* DCC */
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if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
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!(surf->flags & RADEON_SURF_SCANOUT) &&
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!compressed &&
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in->swizzleMode != ADDR_SW_LINEAR &&
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/* TODO: We could support DCC with MSAA. */
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in->numSamples == 1) {
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ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
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ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
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din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
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dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
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din.dccKeyFlags.pipeAligned = 1;
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din.dccKeyFlags.rbAligned = 1;
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din.colorFlags = in->flags;
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din.resourceType = in->resourceType;
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din.swizzleMode = in->swizzleMode;
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din.bpp = in->bpp;
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din.unalignedWidth = in->width;
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din.unalignedHeight = in->height;
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din.numSlices = in->numSlices;
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din.numFrags = in->numFrags;
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din.numMipLevels = in->numMipLevels;
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din.dataSurfaceSize = out.surfSize;
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ret = Addr2ComputeDccInfo(ws->addrlib, &din, &dout);
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if (ret != ADDR_OK)
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return ret;
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surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
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surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
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surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
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surf->dcc_size = dout.dccRamSize;
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surf->dcc_alignment = dout.dccRamBaseAlign;
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}
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/* FMASK */
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if (in->numSamples > 1) {
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ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
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ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
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fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
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fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
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ret = gfx9_get_preferred_swizzle_mode(ws, in, true, &fin.swizzleMode);
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if (ret != ADDR_OK)
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return ret;
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fin.unalignedWidth = in->width;
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fin.unalignedHeight = in->height;
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fin.numSlices = in->numSlices;
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fin.numSamples = in->numSamples;
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fin.numFrags = in->numFrags;
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ret = Addr2ComputeFmaskInfo(ws->addrlib, &fin, &fout);
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if (ret != ADDR_OK)
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return ret;
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surf->u.gfx9.fmask.swizzle_mode = in->swizzleMode;
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surf->u.gfx9.fmask.epitch = fout.pitch - 1;
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surf->u.gfx9.fmask_size = fout.fmaskBytes;
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surf->u.gfx9.fmask_alignment = fout.baseAlign;
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}
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/* CMASK */
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if (in->swizzleMode != ADDR_SW_LINEAR) {
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ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
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ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
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cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
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cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
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cin.cMaskFlags.pipeAligned = 1;
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cin.cMaskFlags.rbAligned = 1;
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cin.colorFlags = in->flags;
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cin.resourceType = in->resourceType;
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cin.unalignedWidth = in->width;
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cin.unalignedHeight = in->height;
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cin.numSlices = in->numSlices;
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if (in->numSamples > 1)
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cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
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else
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cin.swizzleMode = in->swizzleMode;
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ret = Addr2ComputeCmaskInfo(ws->addrlib, &cin, &cout);
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if (ret != ADDR_OK)
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return ret;
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surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
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surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
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surf->u.gfx9.cmask_size = cout.cmaskBytes;
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surf->u.gfx9.cmask_alignment = cout.baseAlign;
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}
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}
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return 0;
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}
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static int gfx9_surface_init(struct radeon_winsys *rws,
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const struct pipe_resource *tex,
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unsigned flags, unsigned bpe,
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enum radeon_surf_mode mode,
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struct radeon_surf *surf)
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{
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struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
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bool compressed;
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ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
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int r;
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assert(!(flags & RADEON_SURF_FMASK));
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r = amdgpu_surface_sanity(tex);
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if (r)
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return r;
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AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
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surf->blk_w = util_format_get_blockwidth(tex->format);
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surf->blk_h = util_format_get_blockheight(tex->format);
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surf->bpe = bpe;
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surf->flags = flags;
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compressed = surf->blk_w == 4 && surf->blk_h == 4;
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/* The format must be set correctly for the allocation of compressed
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* textures to work. In other cases, setting the bpp is sufficient. */
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if (compressed) {
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switch (bpe) {
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case 8:
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AddrSurfInfoIn.format = ADDR_FMT_BC1;
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break;
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case 16:
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AddrSurfInfoIn.format = ADDR_FMT_BC3;
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break;
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default:
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assert(0);
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}
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} else {
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AddrSurfInfoIn.bpp = bpe * 8;
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}
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AddrSurfInfoIn.flags.color = !(flags & RADEON_SURF_Z_OR_SBUFFER);
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AddrSurfInfoIn.flags.depth = (flags & RADEON_SURF_ZBUFFER) != 0;
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AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
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AddrSurfInfoIn.flags.texture = 1;
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AddrSurfInfoIn.flags.opt4space = 1;
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AddrSurfInfoIn.numMipLevels = tex->last_level + 1;
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AddrSurfInfoIn.numSamples = tex->nr_samples ? tex->nr_samples : 1;
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AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
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switch (tex->target) {
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case PIPE_TEXTURE_1D:
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case PIPE_TEXTURE_1D_ARRAY:
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AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
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AddrSurfInfoIn.width = tex->width0;
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AddrSurfInfoIn.height = 1;
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AddrSurfInfoIn.numSlices = tex->array_size;
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AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR; /* the only allowed mode */
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break;
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case PIPE_TEXTURE_2D:
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case PIPE_TEXTURE_2D_ARRAY:
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case PIPE_TEXTURE_RECT:
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_CUBE_ARRAY:
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case PIPE_TEXTURE_3D:
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if (tex->target == PIPE_TEXTURE_3D)
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AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
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else
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AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
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AddrSurfInfoIn.width = tex->width0;
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AddrSurfInfoIn.height = tex->height0;
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if (tex->target == PIPE_TEXTURE_3D)
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AddrSurfInfoIn.numSlices = tex->depth0;
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else if (tex->target == PIPE_TEXTURE_CUBE)
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AddrSurfInfoIn.numSlices = 6;
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else
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AddrSurfInfoIn.numSlices = tex->array_size;
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switch (mode) {
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case RADEON_SURF_MODE_LINEAR_ALIGNED:
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assert(tex->nr_samples <= 1);
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assert(!(flags & RADEON_SURF_Z_OR_SBUFFER));
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AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
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break;
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case RADEON_SURF_MODE_1D:
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case RADEON_SURF_MODE_2D:
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r = gfx9_get_preferred_swizzle_mode(ws, &AddrSurfInfoIn, false,
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&AddrSurfInfoIn.swizzleMode);
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if (r)
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return r;
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break;
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default:
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assert(0);
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}
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break;
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default:
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assert(0);
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}
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surf->surf_size = 0;
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surf->dcc_size = 0;
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surf->htile_size = 0;
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surf->u.gfx9.stencil_offset = 0;
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surf->u.gfx9.fmask_size = 0;
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surf->u.gfx9.cmask_size = 0;
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/* Calculate texture layout information. */
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r = gfx9_compute_miptree(ws, surf, compressed, &AddrSurfInfoIn);
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if (r)
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return r;
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/* Calculate texture layout information for stencil. */
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if (flags & RADEON_SURF_SBUFFER) {
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AddrSurfInfoIn.bpp = 8;
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AddrSurfInfoIn.flags.depth = 0;
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AddrSurfInfoIn.flags.stencil = 1;
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r = gfx9_compute_miptree(ws, surf, compressed, &AddrSurfInfoIn);
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if (r)
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return r;
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}
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surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
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surf->num_dcc_levels = surf->dcc_size ? tex->last_level + 1 : 0;
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switch (surf->u.gfx9.surf.swizzle_mode) {
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/* S = standard. */
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case ADDR_SW_256B_S:
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case ADDR_SW_4KB_S:
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case ADDR_SW_64KB_S:
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case ADDR_SW_VAR_S:
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case ADDR_SW_64KB_S_T:
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case ADDR_SW_4KB_S_X:
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case ADDR_SW_64KB_S_X:
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case ADDR_SW_VAR_S_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
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break;
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/* D = display. */
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case ADDR_SW_LINEAR:
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case ADDR_SW_256B_D:
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case ADDR_SW_4KB_D:
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case ADDR_SW_64KB_D:
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case ADDR_SW_VAR_D:
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case ADDR_SW_64KB_D_T:
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case ADDR_SW_4KB_D_X:
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case ADDR_SW_64KB_D_X:
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case ADDR_SW_VAR_D_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
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break;
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/* R = rotated. */
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case ADDR_SW_256B_R:
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case ADDR_SW_4KB_R:
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case ADDR_SW_64KB_R:
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case ADDR_SW_VAR_R:
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case ADDR_SW_64KB_R_T:
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case ADDR_SW_4KB_R_X:
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case ADDR_SW_64KB_R_X:
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case ADDR_SW_VAR_R_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
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break;
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/* Z = depth. */
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case ADDR_SW_4KB_Z:
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case ADDR_SW_64KB_Z:
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case ADDR_SW_VAR_Z:
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case ADDR_SW_64KB_Z_T:
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case ADDR_SW_4KB_Z_X:
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case ADDR_SW_64KB_Z_X:
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case ADDR_SW_VAR_Z_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
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break;
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default:
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assert(0);
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}
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return 0;
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}
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void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
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{
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if (ws->info.chip_class >= GFX9)
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ws->base.surface_init = NULL;
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ws->base.surface_init = gfx9_surface_init;
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else
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ws->base.surface_init = gfx6_surface_init;
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}
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