fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-04 09:48:07 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-01-12 02:47:05 +01:00
parent 493de7f935
commit 9b365d497a
1 changed files with 11 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -40,6 +40,8 @@
#include <stdio.h>
#include <sys/stat.h>
#include "amd/common/amdgpu_id.h"
#include "amd/common/sid.h"
#include "amd/common/gfx9d.h"
#define CIK_TILE_MODE_COLOR_2D 14
@ -352,8 +354,15 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
ws->info.num_render_backends = ws->amdinfo.rb_pipes;
ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
if (ws->info.chip_class == GFX9) {
ws->info.num_tile_pipes = 1 << G_0098F8_NUM_PIPES(ws->amdinfo.gb_addr_cfg);
ws->info.pipe_interleave_bytes =
256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(ws->amdinfo.gb_addr_cfg);
} else {
ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
ws->info.pipe_interleave_bytes =
256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(ws->amdinfo.gb_addr_cfg);
}
ws->info.has_virtual_memory = true;
ws->info.has_sdma = dma.available_rings != 0;