The IO semantics already contain all the information needed
for VS inputs, so there is no need use driver locations.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28553>
They are not needed anymore.
Both NIR and RADV shader info can be fully deduced from I/O
intrinsics, so there is no need to keep the variables.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28506>
This commit does two things at once, which cannot be split
into two commits because otherwise the driver would regress
in-between the two.
Change radv_nir_shader_info_pass so that it uses I/O intrinsics
instead of I/O variables for determining FS information.
Also eliminate gaps between input slots caused by unused input
variables. To this end, we use nir_recompute_io_bases after
nir_lower_io instead of assigning driver locations before it.
As part of this, we can now omit a clip/cull input when only
the second one is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28506>
Using the same SGPR bitfield in TCS and TES will simplify driver
code and make RADV consistent with RadeonSI.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
We no longer need to emit store_output intrinsics at the
end of the shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
TCS epilogs are not needed anymore because the TCS can implement
dynamic states by itself now.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
This allows the TCS to read the primitive mode and whether
TES reads the tess factors, from an SGPR arg, which lets it
decide how to store them at runtime.
For linked shaders, the conditions will be constant and
NIR optimizations can delete the dead CF.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
For linked shaders, the information is available as constant,
while for unlinked shaders, the info is in a SGPR arg.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
This will allow us to more accurately determine the
input and output strides, because the I/O locations mapped
by RADV don't match the locations in NIR.
As a result, ESO will use less LDS.
It also fixes the per-patch output stride of tess control
shaders, because previously we omitted tess factors from them.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28021>
We can gather the args used by all other stages and use that to optimize
the traversal shader.
Totals from 4 (1.06% of 379) affected shaders:
Instrs: 2912 -> 2864 (-1.65%)
CodeSize: 15424 -> 15232 (-1.24%)
Latency: 69342 -> 69074 (-0.39%)
InvThroughput: 11558 -> 11512 (-0.40%)
Copies: 712 -> 676 (-5.06%)
Branches: 152 -> 148 (-2.63%)
PreVGPRs: 324 -> 316 (-2.47%)
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
This prevents potential app bugs causing GPU hangs and other issues.
Note that the draw ID is undefined in mesh shaders when also
using a task shader.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27879>
This only dumps the begin tokens. Tokens are written to a buffer
containing a 12 byte header at the beginning.
We use an intermediate format for the ray history tokens because the RRA
format is very inefficient.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25548>
For storing the per-stage key information like robustness etc. This
will fit well with ESO as well.
For pipelines, they are copied from radv_pipeline_key, similarly to
the radv_pipeline_layout/radv_shader_layout pair.
This will also allow us to kill radv_pipeline_key for compute/rt
pipelines.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
