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ac/nir/tess: Remove superfluous args for reserved TCS outputs.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28487>
This commit is contained in:
Timur Kristóf 2024-03-30 23:45:15 +01:00 • committed by Marge Bot
parent ae8a954048
commit 9faabdd5dd
4 changed files with 1 additions and 8 deletions
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2
src/amd/common/ac_nir.h
View file

@ -132,8 +132,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
enum amd_gfx_level gfx_level,
uint64_t tes_inputs_read,
uint32_t tes_patch_inputs_read,
unsigned num_reserved_tcs_outputs,
unsigned num_reserved_tcs_patch_outputs,
unsigned wave_size,
bool no_inputs_in_lds,
bool pass_tessfactors_by_reg);

2
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View file

@ -947,8 +947,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
enum amd_gfx_level gfx_level,
uint64_t tes_inputs_read,
uint32_t tes_patch_inputs_read,
unsigned num_reserved_tcs_outputs,
unsigned num_reserved_tcs_patch_outputs,
unsigned wave_size,
bool no_inputs_in_lds,
bool pass_tessfactors_by_reg)

3
src/amd/vulkan/nir/radv_nir_lower_io.c
View file

@ -154,8 +154,7 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s
} else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq);
NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, pdev->info.gfx_level, info->tcs.tes_inputs_read,
info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs,
info->wave_size, false, false);
info->tcs.tes_patch_inputs_read, info->wave_size, false, false);
return true;
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {

2
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -1795,8 +1795,6 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir,
NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, si_map_io_driver_location,
sel->screen->info.gfx_level,
~0ULL, ~0U, /* no TES inputs filter */
util_last_bit64(sel->info.outputs_written_before_tes_gs),
util_last_bit64(sel->info.patch_outputs_written),
shader->wave_size,
/* ALL TCS inputs are passed by register. */
key->ge.opt.same_patch_vertices &&