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ac/nir/tess: Remove dead code that was meant for epilogs.

Browse source 
We no longer need to emit store_output intrinsics at the
end of the shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
This commit is contained in:
Timur Kristóf 2024-03-30 02:32:51 +01:00
parent b34e99d021
commit 96ee0d6711
4 changed files with 10 additions and 57 deletions
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4
src/amd/common/ac_nir.h
View file

@ -129,9 +129,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
unsigned num_reserved_tcs_patch_outputs,
unsigned wave_size,
bool no_inputs_in_lds,
bool pass_tessfactors_by_reg,
bool emit_tess_factor_write,
bool emit_tess_factor_output);
bool pass_tessfactors_by_reg);
void
ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,

57
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View file

@ -699,15 +699,8 @@ hs_if_invocation_id_zero(nir_builder *b)
static void
hs_finale(nir_shader *shader,
lower_tess_io_state *st,
bool store_tess_factors,
bool write_tess_factor_outputs)
lower_tess_io_state *st)
{
if (!store_tess_factors && !write_tess_factor_outputs)
return;
assert(!store_tess_factors || !write_tess_factor_outputs);
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
assert(impl);
nir_block *last_block = nir_impl_last_block(impl);
@ -724,13 +717,10 @@ hs_finale(nir_shader *shader,
}
/* Only the 1st invocation of each patch needs to access VRAM and/or LDS. */
nir_if *if_invocation_id_zero = NULL;
if (!st->tcs_pass_tessfactors_by_reg || store_tess_factors)
if_invocation_id_zero = hs_if_invocation_id_zero(b);
nir_if *if_invocation_id_zero = hs_if_invocation_id_zero(b);
{
tess_levels tessfactors = hs_load_tess_levels(b, st);
tess_levels tessfactors = hs_load_tess_levels(b, st);
if (store_tess_factors) {
if (st->gfx_level <= GFX8)
hs_store_dynamic_control_word_gfx6(b);
@ -760,38 +750,7 @@ hs_finale(nir_shader *shader,
nir_pop_if(b, if_tes_reads_tf);
}
if (if_invocation_id_zero) {
/* Make sure that the tess factor definitions are available in top-level CF. */
nir_push_else(b, if_invocation_id_zero);
nir_def *outer_undef = tessfactors.outer ? nir_undef(b, tessfactors.outer->num_components, 32) : NULL;
nir_def *inner_undef = tessfactors.inner ? nir_undef(b, tessfactors.inner->num_components, 32) : NULL;
nir_pop_if(b, if_invocation_id_zero);
if (tessfactors.outer)
tessfactors.outer = nir_if_phi(b, tessfactors.outer, outer_undef);
if (tessfactors.inner)
tessfactors.inner = nir_if_phi(b, tessfactors.inner, inner_undef);
}
if (write_tess_factor_outputs) {
/* Write tess factor output variables, these are passed to the TCS epilog.
* This needs to be in top-level CF, otherwise ACO will have trouble with it
* because nir_lower_io_to_temporaries doesn't work for TCS.
*/
if (st->tcs_tess_level_outer_mask) {
nir_store_output(b, tessfactors.outer, nir_imm_int(b, 0),
.base = st->tcs_tess_level_outer_base,
.write_mask = st->tcs_tess_level_outer_mask,
.io_semantics.location = VARYING_SLOT_TESS_LEVEL_OUTER);
}
if (st->tcs_tess_level_inner_mask) {
nir_store_output(b, tessfactors.inner, nir_imm_int(b, 0),
.base = st->tcs_tess_level_inner_base,
.write_mask = st->tcs_tess_level_inner_mask,
.io_semantics.location = VARYING_SLOT_TESS_LEVEL_INNER);
}
}
nir_pop_if(b, if_invocation_id_zero);
nir_metadata_preserve(impl, nir_metadata_none);
}
@ -892,9 +851,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
unsigned num_reserved_tcs_patch_outputs,
unsigned wave_size,
bool no_inputs_in_lds,
bool pass_tessfactors_by_reg,
bool emit_tess_factor_write,
bool emit_tess_factor_output)
bool pass_tessfactors_by_reg)
{
assert(shader->info.stage == MESA_SHADER_TESS_CTRL);
@ -923,7 +880,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
lower_hs_output_access,
&state);
hs_finale(shader, &state, emit_tess_factor_write, emit_tess_factor_output);
hs_finale(shader, &state);
}
void

2
src/amd/vulkan/nir/radv_nir_lower_io.c
View file

@ -152,7 +152,7 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s
NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq);
NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, device->physical_device->rad_info.gfx_level,
info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs,
info->tcs.num_linked_patch_outputs, info->wave_size, false, false, true, false);
info->tcs.num_linked_patch_outputs, info->wave_size, false, false);
return true;
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {

4
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -1801,9 +1801,7 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir,
/* ALL TCS inputs are passed by register. */
key->ge.opt.same_patch_vertices &&
!(sel->info.base.inputs_read & ~sel->info.tcs_vgpr_only_inputs),
sel->info.tessfactors_are_def_in_all_invocs,
true,
false);
sel->info.tessfactors_are_def_in_all_invocs);
return true;
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, si_map_io_driver_location);