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radv: Reuse TCS offchip layout between TCS and TES.

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Using the same SGPR bitfield in TCS and TES will simplify driver
code and make RADV consistent with RadeonSI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
This commit is contained in:
Timur Kristóf 2024-04-01 01:23:44 +02:00 • committed by Marge Bot
parent 4b0b0e675c
commit 3223650bad
5 changed files with 18 additions and 41 deletions
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32
src/amd/vulkan/nir/radv_nir_lower_abi.c
View file

@ -95,12 +95,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
if (s->info->num_tess_patches) {
replacement = nir_imm_int(b, s->info->num_tess_patches);
} else {
if (stage == MESA_SHADER_TESS_CTRL) {
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
replacement = nir_iadd_imm_nuw(b, n, 1);
} else {
replacement = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_NUM_PATCHES);
}
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
replacement = nir_iadd_imm_nuw(b, n, 1);
}
break;
case nir_intrinsic_load_tcs_tess_levels_to_tes_amd:
@ -183,7 +179,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
if (s->info->tes.tcs_vertices_out) {
replacement = nir_imm_int(b, s->info->tes.tcs_vertices_out);
} else {
replacement = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_TCS_VERTICES_OUT);
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_OUT_PATCH_CP);
replacement = nir_iadd_imm_nuw(b, n, 1);
}
} else
unreachable("invalid tessellation shader stage");
@ -318,15 +315,12 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
out_vertices_per_patch = nir_imm_int(b, s->info->tcs.tcs_vertices_out);
} else {
if (s->info->inputs_linked) {
out_vertices_per_patch = nir_imm_int(b, s->info->tes.tcs_vertices_out);
num_tcs_outputs = nir_imm_int(b, s->info->tes.num_linked_inputs);
} else {
num_tcs_outputs = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_NUM_TCS_OUTPUTS);
}
if (s->info->tes.tcs_vertices_out) {
out_vertices_per_patch = nir_imm_int(b, s->info->tes.tcs_vertices_out);
} else {
out_vertices_per_patch = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_TCS_VERTICES_OUT);
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_OUT_PATCH_CP);
out_vertices_per_patch = nir_iadd_imm_nuw(b, n, 1);
num_tcs_outputs = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS);
}
}
@ -337,14 +331,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
unsigned num_patches = s->info->num_tess_patches;
replacement = nir_imul_imm(b, per_vertex_output_patch_size, num_patches);
} else {
nir_def *num_patches;
if (stage == MESA_SHADER_TESS_CTRL) {
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
num_patches = nir_iadd_imm_nuw(b, n, 1);
} else {
num_patches = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_NUM_PATCHES);
}
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
nir_def *num_patches = nir_iadd_imm_nuw(b, n, 1);
replacement = nir_imul(b, per_vertex_output_patch_size, num_patches);
}
break;

10
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2701,15 +2701,11 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer)
base_reg = tcs->info.user_data_0;
radeon_set_sh_reg(cmd_buffer->cs, base_reg + offchip->sgpr_idx * 4, tcs_offchip_layout);
const struct radv_userdata_info *num_patches = radv_get_user_sgpr(tes, AC_UD_TES_STATE);
assert(num_patches->sgpr_idx != -1 && num_patches->num_sgprs == 1);
const unsigned tes_state = SET_SGPR_FIELD(TES_STATE_NUM_PATCHES, cmd_buffer->state.tess_num_patches) |
SET_SGPR_FIELD(TES_STATE_TCS_VERTICES_OUT, tcs->info.tcs.tcs_vertices_out) |
SET_SGPR_FIELD(TES_STATE_NUM_TCS_OUTPUTS, tcs->info.tcs.num_linked_outputs);
const struct radv_userdata_info *tes_offchip = radv_get_user_sgpr(tes, AC_UD_TCS_OFFCHIP_LAYOUT);
assert(tes_offchip->sgpr_idx != -1 && tes_offchip->num_sgprs == 1);
base_reg = tes->info.user_data_0;
radeon_set_sh_reg(cmd_buffer->cs, base_reg + num_patches->sgpr_idx * 4, tes_state);
radeon_set_sh_reg(cmd_buffer->cs, base_reg + tes_offchip->sgpr_idx * 4, tcs_offchip_layout);
}
static void

3
src/amd/vulkan/radv_shader.h
View file

@ -241,8 +241,7 @@ enum radv_ud_index {
/* We might not know the previous stage when compiling a geometry shader, so we just
* declare both TES and VS user SGPRs.
*/
AC_UD_TES_STATE = AC_UD_VS_MAX_UD,
AC_UD_TES_MAX_UD,
AC_UD_TES_MAX_UD = AC_UD_TCS_MAX_UD,
AC_UD_MAX_UD = AC_UD_CS_MAX_UD,
};

8
src/amd/vulkan/radv_shader_args.c
View file

@ -456,7 +456,7 @@ declare_unmerged_vs_tes_gs_args(const enum amd_gfx_level gfx_level, const struct
declare_global_input_sgprs(info, user_sgpr_info, args);
add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
add_ud_arg(args, 1, AC_ARG_INT, &args->tes_state, AC_UD_TES_STATE);
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT);
add_ud_arg(args, 1, AC_ARG_INT, &args->shader_query_state, AC_UD_SHADER_QUERY_STATE);
if (info->is_ngg) {
@ -493,7 +493,7 @@ declare_unmerged_vs_tes_gs_args(const enum amd_gfx_level gfx_level, const struct
ac_add_preserved(&args->ac, &args->ac.push_constants);
ac_add_preserved(&args->ac, &args->streamout_buffers);
ac_add_preserved(&args->ac, &args->ac.view_index);
ac_add_preserved(&args->ac, &args->tes_state);
ac_add_preserved(&args->ac, &args->tcs_offchip_layout);
ac_add_preserved(&args->ac, &args->shader_query_state);
if (info->is_ngg)
ac_add_preserved(&args->ac, &args->ngg_provoking_vtx);
@ -719,7 +719,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
if (radv_tes_needs_state_sgpr(info))
add_ud_arg(args, 1, AC_ARG_INT, &args->tes_state, AC_UD_TES_STATE);
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT);
if (info->tes.as_es) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
@ -771,7 +771,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
}
if (previous_stage == MESA_SHADER_TESS_EVAL && radv_tes_needs_state_sgpr(info))
add_ud_arg(args, 1, AC_ARG_INT, &args->tes_state, AC_UD_TES_STATE);
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT);
if (previous_stage == MESA_SHADER_VERTEX && info->vs.dynamic_num_verts_per_prim)
add_ud_arg(args, 1, AC_ARG_INT, &args->num_verts_per_prim, AC_UD_NUM_VERTS_PER_PRIM);

6
src/amd/vulkan/radv_shader_args.h
View file

@ -77,12 +77,6 @@ struct radv_shader_args {
*/
struct ac_arg tcs_offchip_layout;
/* TES */
/* # [0:7] = the number of tessellation patches
* # [8:15] = the number of TCS vertices output
*/
struct ac_arg tes_state;
/* GS */
struct ac_arg vgt_esgs_ring_itemsize;