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radv: remove radv_physical_device::instance

Browse source 
Get the instance object using the base object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28500>
This commit is contained in:
Samuel Pitoiset 2024-04-01 14:51:07 +02:00 • committed by Marge Bot
parent e2c29c9bb6
commit b35b2718be
22 changed files with 283 additions and 188 deletions
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4
src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
View file

@ -502,10 +502,12 @@ void
radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, const struct radv_shader_stage *stage)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
apply_layout_state state = {
.gfx_level = pdev->info.gfx_level,
.address32_hi = pdev->info.address32_hi,
.disable_aniso_single_level = pdev->instance->drirc.disable_aniso_single_level,
.disable_aniso_single_level = instance->drirc.disable_aniso_single_level,
.has_image_load_dcc_bug = pdev->info.has_image_load_dcc_bug,
.disable_tg4_trunc_coord = !pdev->info.conformant_trunc_coord && !device->disable_trunc_coord,
.args = &stage->args,

3
src/amd/vulkan/nir/radv_nir_lower_ray_queries.c
View file

@ -649,6 +649,7 @@ bool
radv_nir_lower_ray_queries(struct nir_shader *shader, struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_instance *instance = radv_physical_device_instance(pdev);
bool progress = false;
struct hash_table *query_ht = _mesa_pointer_hash_table_create(NULL);
@ -711,7 +712,7 @@ radv_nir_lower_ray_queries(struct nir_shader *shader, struct radv_device *device
lower_rq_generate_intersection(&builder, index, intrinsic, vars);
break;
case nir_intrinsic_rq_initialize:
lower_rq_initialize(&builder, index, intrinsic, vars, pdev->instance);
lower_rq_initialize(&builder, index, intrinsic, vars, instance);
break;
case nir_intrinsic_rq_load:
new_dest = lower_rq_load(device, &builder, index, intrinsic, vars);

12
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -812,6 +812,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (unlikely(device->sqtt.bo) && !dgc) {
radeon_check_space(device->ws, cmd_buffer->cs, 2);
@ -820,7 +821,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu
radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
}
if (pdev->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
if (instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
enum rgp_flush_bits sqtt_flush_bits = 0;
assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
@ -4187,10 +4188,11 @@ radv_emit_alpha_to_coverage_enable(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
unsigned db_alpha_to_mask = 0;
if (pdev->instance->debug_flags & RADV_DEBUG_NO_ATOC_DITHERING) {
if (instance->debug_flags & RADV_DEBUG_NO_ATOC_DITHERING) {
db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
S_028B70_OFFSET_ROUND(0);
@ -6117,7 +6119,8 @@ radv_bind_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
RADV_FROM_HANDLE(radv_pipeline_layout, layout, pBindDescriptorSetsInfo->layout);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const bool no_dynamic_bounds = pdev->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const bool no_dynamic_bounds = instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point);
unsigned dyn_idx = 0;
@ -10693,8 +10696,9 @@ radv_trace_rays(struct radv_cmd_buffer *cmd_buffer, VkTraceRaysIndirectCommand2K
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (pdev->instance->debug_flags & RADV_DEBUG_NO_RT)
if (instance->debug_flags & RADV_DEBUG_NO_RT)
return;
if (unlikely(device->rra_trace.ray_history_buffer))

26
src/amd/vulkan/radv_debug.c
View file

@ -471,6 +471,7 @@ radv_dump_queue_state(struct radv_queue *queue, const char *dump_dir, FILE *f)
{
struct radv_device *device = radv_queue_device(queue);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
enum amd_ip_type ring = radv_queue_ring(queue);
struct radv_pipeline *pipeline;
@ -509,7 +510,7 @@ radv_dump_queue_state(struct radv_queue *queue, const char *dump_dir, FILE *f)
MESA_SHADER_COMPUTE, dump_dir, f);
}
if (!(pdev->instance->debug_flags & RADV_DEBUG_NO_UMR)) {
if (!(instance->debug_flags & RADV_DEBUG_NO_UMR)) {
struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
enum amd_gfx_level gfx_level = pdev->info.gfx_level;
unsigned num_waves = ac_get_wave_info(gfx_level, &pdev->info, waves);
@ -597,12 +598,13 @@ void
radv_dump_enabled_options(const struct radv_device *device, FILE *f)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint64_t mask;
if (pdev->instance->debug_flags) {
if (instance->debug_flags) {
fprintf(f, "Enabled debug options: ");
mask = pdev->instance->debug_flags;
mask = instance->debug_flags;
while (mask) {
int i = u_bit_scan64(&mask);
fprintf(f, "%s, ", radv_get_debug_option_name(i));
@ -610,10 +612,10 @@ radv_dump_enabled_options(const struct radv_device *device, FILE *f)
fprintf(f, "\n");
}
if (pdev->instance->perftest_flags) {
if (instance->perftest_flags) {
fprintf(f, "Enabled perftest options: ");
mask = pdev->instance->perftest_flags;
mask = instance->perftest_flags;
while (mask) {
int i = u_bit_scan64(&mask);
fprintf(f, "%s, ", radv_get_perftest_option_name(i));
@ -626,7 +628,7 @@ static void
radv_dump_app_info(const struct radv_device *device, FILE *f)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = pdev->instance;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
fprintf(f, "Application name: %s\n", instance->vk.app_info.app_name);
fprintf(f, "Application version: %d\n", instance->vk.app_info.app_version);
@ -755,6 +757,7 @@ radv_check_gpu_hangs(struct radv_queue *queue, const struct radv_winsys_submit_i
#ifndef _WIN32
struct radv_device *device = radv_queue_device(queue);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const bool save_hang_report = !device->vk.enabled_features.deviceFaultVendorBinary;
struct radv_winsys_gpuvm_fault_info fault_info = {0};
@ -814,11 +817,11 @@ radv_check_gpu_hangs(struct radv_queue *queue, const struct radv_winsys_submit_i
radv_dump_queue_state(queue, dump_dir, f);
break;
case RADV_DEVICE_FAULT_CHUNK_UMR_WAVES:
if (!(pdev->instance->debug_flags & RADV_DEBUG_NO_UMR))
if (!(instance->debug_flags & RADV_DEBUG_NO_UMR))
radv_dump_umr_waves(queue, f);
break;
case RADV_DEVICE_FAULT_CHUNK_UMR_RING:
if (!(pdev->instance->debug_flags & RADV_DEBUG_NO_UMR))
if (!(instance->debug_flags & RADV_DEBUG_NO_UMR))
radv_dump_umr_ring(queue, f);
break;
case RADV_DEVICE_FAULT_CHUNK_REGISTERS:
@ -1098,6 +1101,7 @@ radv_GetDeviceFaultInfoEXT(VkDevice _device, VkDeviceFaultCountsEXT *pFaultCount
struct radv_winsys_gpuvm_fault_info fault_info = {0};
RADV_FROM_HANDLE(radv_device, device, _device);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
bool vm_fault_occurred = false;
/* Query if a GPUVM fault happened. */
@ -1117,10 +1121,10 @@ radv_GetDeviceFaultInfoEXT(VkDevice _device, VkDeviceFaultCountsEXT *pFaultCount
hdr.driverVersion = pdev->vk.properties.driverVersion;
memcpy(hdr.pipelineCacheUUID, pdev->cache_uuid, VK_UUID_SIZE);
hdr.applicationNameOffset = 0;
hdr.applicationVersion = pdev->instance->vk.app_info.app_version;
hdr.applicationVersion = instance->vk.app_info.app_version;
hdr.engineNameOffset = 0;
hdr.engineVersion = pdev->instance->vk.app_info.engine_version;
hdr.apiVersion = pdev->instance->vk.app_info.api_version;
hdr.engineVersion = instance->vk.app_info.engine_version;
hdr.apiVersion = instance->vk.app_info.api_version;
pFaultCounts->vendorBinarySize = sizeof(hdr) + strlen(device->gpu_hang_report);
if (pFaultInfo) {

4
src/amd/vulkan/radv_debug.h
View file

@ -115,7 +115,9 @@ ALWAYS_INLINE static bool
radv_device_fault_detection_enabled(const struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
return pdev->instance->debug_flags & RADV_DEBUG_HANG;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return instance->debug_flags & RADV_DEBUG_HANG;
}
#endif

3
src/amd/vulkan/radv_descriptor_set.c
View file

@ -908,11 +908,12 @@ radv_create_descriptor_pool(struct radv_device *device, const VkDescriptorPoolCr
if (bo_size) {
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (!(pCreateInfo->flags & VK_DESCRIPTOR_POOL_CREATE_HOST_ONLY_BIT_EXT)) {
enum radeon_bo_flag flags = RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT;
if (pdev->instance->drirc.zero_vram)
if (instance->drirc.zero_vram)
flags |= RADEON_FLAG_ZERO_VRAM;
VkResult result = radv_bo_create(device, bo_size, 32, RADEON_DOMAIN_VRAM, flags, RADV_BO_PRIORITY_DESCRIPTOR,

72
src/amd/vulkan/radv_device.c
View file

@ -187,12 +187,13 @@ static VkResult
radv_device_init_vs_prologs(struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (!radv_shader_part_cache_init(&device->vs_prologs, &vs_prolog_ops))
return vk_error(pdev->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
/* don't pre-compile prologs if we want to print them */
if (pdev->instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS)
if (instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS)
return VK_SUCCESS;
struct radv_vs_prolog_key key;
@ -208,7 +209,7 @@ radv_device_init_vs_prologs(struct radv_device *device)
device->simple_vs_prologs[i - 1] = radv_create_vs_prolog(device, &key);
if (!device->simple_vs_prologs[i - 1])
return vk_error(pdev->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
return vk_error(instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
unsigned idx = 0;
@ -220,7 +221,7 @@ radv_device_init_vs_prologs(struct radv_device *device)
struct radv_shader_part *prolog = radv_create_vs_prolog(device, &key);
if (!prolog)
return vk_error(pdev->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
return vk_error(instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
assert(idx == radv_instance_rate_prolog_index(num_attributes, key.instance_rate_inputs));
device->instance_rate_vs_prologs[idx++] = prolog;
@ -558,6 +559,7 @@ add_entrypoints(struct dispatch_table_builder *b, const struct vk_device_entrypo
static void
init_dispatch_tables(struct radv_device *device, struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct dispatch_table_builder b = {0};
b.tables[RADV_DEVICE_DISPATCH_TABLE] = &device->vk.dispatch_table;
b.tables[RADV_ANNOTATE_DISPATCH_TABLE] = &device->layer_dispatch.annotate;
@ -567,26 +569,26 @@ init_dispatch_tables(struct radv_device *device, struct radv_physical_device *pd
b.tables[RADV_RMV_DISPATCH_TABLE] = &device->layer_dispatch.rmv;
b.tables[RADV_CTX_ROLL_DISPATCH_TABLE] = &device->layer_dispatch.ctx_roll;
bool gather_ctx_rolls = pdev->instance->vk.trace_mode & RADV_TRACE_MODE_CTX_ROLLS;
bool gather_ctx_rolls = instance->vk.trace_mode & RADV_TRACE_MODE_CTX_ROLLS;
if (radv_device_fault_detection_enabled(device) || gather_ctx_rolls)
add_entrypoints(&b, &annotate_device_entrypoints, RADV_ANNOTATE_DISPATCH_TABLE);
if (!strcmp(pdev->instance->drirc.app_layer, "metroexodus")) {
if (!strcmp(instance->drirc.app_layer, "metroexodus")) {
add_entrypoints(&b, &metro_exodus_device_entrypoints, RADV_APP_DISPATCH_TABLE);
} else if (!strcmp(pdev->instance->drirc.app_layer, "rage2")) {
} else if (!strcmp(instance->drirc.app_layer, "rage2")) {
add_entrypoints(&b, &rage2_device_entrypoints, RADV_APP_DISPATCH_TABLE);
} else if (!strcmp(pdev->instance->drirc.app_layer, "quanticdream")) {
} else if (!strcmp(instance->drirc.app_layer, "quanticdream")) {
add_entrypoints(&b, &quantic_dream_device_entrypoints, RADV_APP_DISPATCH_TABLE);
}
if (pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP)
if (instance->vk.trace_mode & RADV_TRACE_MODE_RGP)
add_entrypoints(&b, &sqtt_device_entrypoints, RADV_RGP_DISPATCH_TABLE);
if ((pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RRA) && radv_enable_rt(pdev, false))
if ((instance->vk.trace_mode & RADV_TRACE_MODE_RRA) && radv_enable_rt(pdev, false))
add_entrypoints(&b, &rra_device_entrypoints, RADV_RRA_DISPATCH_TABLE);
#ifndef _WIN32
if (pdev->instance->vk.trace_mode & VK_TRACE_MODE_RMV)
if (instance->vk.trace_mode & VK_TRACE_MODE_RMV)
add_entrypoints(&b, &rmv_device_entrypoints, RADV_RMV_DISPATCH_TABLE);
#endif
@ -604,10 +606,11 @@ capture_trace(VkQueue _queue)
RADV_FROM_HANDLE(radv_queue, queue, _queue);
struct radv_device *device = radv_queue_device(queue);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkResult result = VK_SUCCESS;
if (pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RRA)
if (instance->vk.trace_mode & RADV_TRACE_MODE_RRA)
device->rra_trace.triggered = true;
if (device->vk.memory_trace_data.is_enabled) {
@ -617,10 +620,10 @@ capture_trace(VkQueue _queue)
simple_mtx_unlock(&device->vk.memory_trace_data.token_mtx);
}
if (pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP)
if (instance->vk.trace_mode & RADV_TRACE_MODE_RGP)
device->sqtt_triggered = true;
if (pdev->instance->vk.trace_mode & RADV_TRACE_MODE_CTX_ROLLS) {
if (instance->vk.trace_mode & RADV_TRACE_MODE_CTX_ROLLS) {
char filename[2048];
time_t t = time(NULL);
struct tm now = *localtime(&t);
@ -671,6 +674,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
const VkAllocationCallbacks *pAllocator, VkDevice *pDevice)
{
RADV_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
struct radv_instance *instance = radv_physical_device_instance(pdev);
VkResult result;
struct radv_device *device;
@ -690,9 +694,9 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
}
}
device = vk_zalloc2(&pdev->instance->vk.alloc, pAllocator, sizeof(*device), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
device = vk_zalloc2(&instance->vk.alloc, pAllocator, sizeof(*device), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
if (!device)
return vk_error(pdev->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
result = vk_device_init(&device->vk, &pdev->vk, NULL, pCreateInfo, pAllocator);
if (result != VK_SUCCESS) {
@ -721,7 +725,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
* from the descriptor set anymore, so we have to use a global BO list.
*/
device->use_global_bo_list =
(pdev->instance->perftest_flags & RADV_PERFTEST_BO_LIST) || device->vk.enabled_features.bufferDeviceAddress ||
(instance->perftest_flags & RADV_PERFTEST_BO_LIST) || device->vk.enabled_features.bufferDeviceAddress ||
device->vk.enabled_features.descriptorIndexing || device->vk.enabled_extensions.EXT_descriptor_indexing ||
device->vk.enabled_extensions.EXT_buffer_device_address ||
device->vk.enabled_extensions.KHR_buffer_device_address ||
@ -738,7 +742,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
device->overallocation_disallowed = overallocation_disallowed;
mtx_init(&device->overallocation_mutex, mtx_plain);
if (pdev->info.register_shadowing_required || pdev->instance->debug_flags & RADV_DEBUG_SHADOW_REGS)
if (pdev->info.register_shadowing_required || instance->debug_flags & RADV_DEBUG_SHADOW_REGS)
device->uses_shadow_regs = true;
/* Create one context per queue priority. */
@ -781,22 +785,22 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
}
device->private_sdma_queue = VK_NULL_HANDLE;
device->shader_use_invisible_vram = (pdev->instance->perftest_flags & RADV_PERFTEST_DMA_SHADERS) &&
device->shader_use_invisible_vram = (instance->perftest_flags & RADV_PERFTEST_DMA_SHADERS) &&
/* SDMA buffer copy is only implemented for GFX7+. */
pdev->info.gfx_level >= GFX7;
result = radv_init_shader_upload_queue(device);
if (result != VK_SUCCESS)
goto fail;
device->pbb_allowed = pdev->info.gfx_level >= GFX9 && !(pdev->instance->debug_flags & RADV_DEBUG_NOBINNING);
device->pbb_allowed = pdev->info.gfx_level >= GFX9 && !(instance->debug_flags & RADV_DEBUG_NOBINNING);
device->disable_trunc_coord = pdev->instance->drirc.disable_trunc_coord;
device->disable_trunc_coord = instance->drirc.disable_trunc_coord;
if (pdev->instance->vk.app_info.engine_name && !strcmp(pdev->instance->vk.app_info.engine_name, "DXVK")) {
if (instance->vk.app_info.engine_name && !strcmp(instance->vk.app_info.engine_name, "DXVK")) {
/* For DXVK 2.3.0 and older, use dualSrcBlend to determine if this is D3D9. */
bool is_d3d9 = !device->vk.enabled_features.dualSrcBlend;
if (pdev->instance->vk.app_info.engine_version > VK_MAKE_VERSION(2, 3, 0))
is_d3d9 = pdev->instance->vk.app_info.app_version & 0x1;
if (instance->vk.app_info.engine_version > VK_MAKE_VERSION(2, 3, 0))
is_d3d9 = instance->vk.app_info.app_version & 0x1;
device->disable_trunc_coord &= !is_d3d9;
}
@ -856,12 +860,12 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
/* Wait for idle after every draw/dispatch to identify the
* first bad call.
*/
pdev->instance->debug_flags |= RADV_DEBUG_SYNC_SHADERS;
instance->debug_flags |= RADV_DEBUG_SYNC_SHADERS;
radv_dump_enabled_options(device, stderr);
}
if (pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP) {
if (instance->vk.trace_mode & RADV_TRACE_MODE_RGP) {
if (pdev->info.gfx_level < GFX8 || pdev->info.gfx_level > GFX11) {
fprintf(stderr, "GPU hardware not supported: refer to "
"the RGP documentation for the list of "
@ -878,10 +882,10 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
"radv: Thread trace support is enabled (initial buffer size: %u MiB, "
"instruction timing: %s, cache counters: %s, queue events: %s).\n",
device->sqtt.buffer_size / (1024 * 1024), radv_is_instruction_timing_enabled() ? "enabled" : "disabled",
radv_spm_trace_enabled(pdev->instance) ? "enabled" : "disabled",
radv_spm_trace_enabled(instance) ? "enabled" : "disabled",
radv_sqtt_queue_events_enabled() ? "enabled" : "disabled");
if (radv_spm_trace_enabled(pdev->instance)) {
if (radv_spm_trace_enabled(instance)) {
if (pdev->info.gfx_level >= GFX10) {
if (!radv_spm_init(device)) {
result = VK_ERROR_INITIALIZATION_FAILED;
@ -894,7 +898,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
}
#ifndef _WIN32
if (pdev->instance->vk.trace_mode & VK_TRACE_MODE_RMV) {
if (instance->vk.trace_mode & VK_TRACE_MODE_RMV) {
struct vk_rmv_device_info info;
memset(&info, 0, sizeof(struct vk_rmv_device_info));
radv_rmv_fill_device_info(pdev, &info);
@ -980,7 +984,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
}
}
if (!(pdev->instance->debug_flags & RADV_DEBUG_NO_IBS))
if (!(instance->debug_flags & RADV_DEBUG_NO_IBS))
radv_create_gfx_config(device);
struct vk_pipeline_cache_create_info info = {.weak_ref = true};
@ -1015,7 +1019,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
}
}
if ((pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RRA) && radv_enable_rt(pdev, false)) {
if ((instance->vk.trace_mode & RADV_TRACE_MODE_RRA) && radv_enable_rt(pdev, false)) {
result = radv_rra_trace_init(device);
if (result != VK_SUCCESS)
goto fail;
@ -1029,8 +1033,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
if (result != VK_SUCCESS)
goto fail_cache;
if (pdev->info.gfx_level == GFX11 && pdev->info.has_dedicated_vram &&
pdev->instance->drirc.force_pstate_peak_gfx11_dgpu) {
if (pdev->info.gfx_level == GFX11 && pdev->info.has_dedicated_vram && instance->drirc.force_pstate_peak_gfx11_dgpu) {
if (!radv_device_acquire_performance_counters(device))
fprintf(stderr, "radv: failed to set pstate to profile_peak.\n");
}
@ -1347,6 +1350,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
struct radv_image_view *iview)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const struct util_format_description *desc;
unsigned ntype, format, swap, endian;
unsigned blend_clamp = 0, blend_bypass = 0;
@ -1529,7 +1533,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
}
}
if (radv_image_has_cmask(iview->image) && !(pdev->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
if (radv_image_has_cmask(iview->image) && !(instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && !iview->disable_dcc_mrt &&

3
src/amd/vulkan/radv_device_memory.c
View file

@ -196,6 +196,7 @@ radv_alloc_memory(struct radv_device *device, const VkMemoryAllocateInfo *pAlloc
}
} else {
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
uint32_t heap_index;
@ -223,7 +224,7 @@ radv_alloc_memory(struct radv_device *device, const VkMemoryAllocateInfo *pAlloc
if (flags_info && flags_info->flags & VK_MEMORY_ALLOCATE_DEVICE_ADDRESS_CAPTURE_REPLAY_BIT)
flags |= RADEON_FLAG_REPLAYABLE;
if (pdev->instance->drirc.zero_vram)
if (instance->drirc.zero_vram)
flags |= RADEON_FLAG_ZERO_VRAM;
if (device->overallocation_disallowed) {

11
src/amd/vulkan/radv_formats.c
View file

@ -701,6 +701,7 @@ static void
radv_physical_device_get_format_properties(struct radv_physical_device *pdev, VkFormat format,
VkFormatProperties3 *out_properties)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkFormatFeatureFlags2 linear = 0, tiled = 0, buffer = 0;
const struct util_format_description *desc = vk_format_description(format);
bool blendable;
@ -747,7 +748,7 @@ radv_physical_device_get_format_properties(struct radv_physical_device *pdev, Vk
tiling |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT;
}
if (pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (format == VK_FORMAT_G8_B8R8_2PLANE_420_UNORM ||
format == VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16)
tiling |= VK_FORMAT_FEATURE_2_VIDEO_DECODE_OUTPUT_BIT_KHR | VK_FORMAT_FEATURE_2_VIDEO_DECODE_DPB_BIT_KHR;
@ -1148,6 +1149,7 @@ static VkFormatFeatureFlags2
radv_get_modifier_flags(struct radv_physical_device *pdev, VkFormat format, uint64_t modifier,
const VkFormatProperties3 *props)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkFormatFeatureFlags2 features;
if (vk_format_is_compressed(format) || vk_format_is_depth_or_stencil(format))
@ -1173,7 +1175,7 @@ radv_get_modifier_flags(struct radv_physical_device *pdev, VkFormat format, uint
radv_is_atomic_format_supported(format))
features &= ~VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT;
if (pdev->instance->debug_flags & (RADV_DEBUG_NO_DCC | RADV_DEBUG_NO_DISPLAY_DCC))
if (instance->debug_flags & (RADV_DEBUG_NO_DCC | RADV_DEBUG_NO_DISPLAY_DCC))
return 0;
}
@ -1672,6 +1674,7 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice,
VkImageFormatProperties2 *base_props)
{
RADV_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const VkPhysicalDeviceExternalImageFormatInfo *external_info = NULL;
VkExternalImageFormatProperties *external_props = NULL;
struct VkAndroidHardwareBufferUsageANDROID *android_usage = NULL;
@ -1771,12 +1774,12 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice,
image_compression_props->imageCompressionFixedRateFlags = VK_IMAGE_COMPRESSION_FIXED_RATE_NONE_EXT;
if (vk_format_is_depth_or_stencil(format)) {
image_compression_props->imageCompressionFlags = (pdev->instance->debug_flags & RADV_DEBUG_NO_HIZ)
image_compression_props->imageCompressionFlags = (instance->debug_flags & RADV_DEBUG_NO_HIZ)
? VK_IMAGE_COMPRESSION_DISABLED_EXT
: VK_IMAGE_COMPRESSION_DEFAULT_EXT;
} else {
image_compression_props->imageCompressionFlags =
((pdev->instance->debug_flags & RADV_DEBUG_NO_DCC) || pdev->info.gfx_level < GFX8)
((instance->debug_flags & RADV_DEBUG_NO_DCC) || pdev->info.gfx_level < GFX8)
? VK_IMAGE_COMPRESSION_DISABLED_EXT
: VK_IMAGE_COMPRESSION_DEFAULT_EXT;
}

37
src/amd/vulkan/radv_image.c
View file

@ -142,8 +142,9 @@ static bool
radv_image_use_fast_clear_for_image_early(const struct radv_device *device, const struct radv_image *image)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (pdev->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)
if (instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)
return true;
if (image->vk.samples <= 1 && image->vk.extent.width * image->vk.extent.height <= 512 * 512) {
@ -162,8 +163,9 @@ static bool
radv_image_use_fast_clear_for_image(const struct radv_device *device, const struct radv_image *image)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (pdev->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)
if (instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)
return true;
return radv_image_use_fast_clear_for_image_early(device, image) && (image->exclusive ||
@ -247,6 +249,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
VkFormat format, bool *sign_reinterpret)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* DCC (Delta Color Compression) is only available for GFX8+. */
if (pdev->info.gfx_level < GFX8)
@ -255,7 +258,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
const VkImageCompressionControlEXT *compression =
vk_find_struct_const(pCreateInfo->pNext, IMAGE_COMPRESSION_CONTROL_EXT);
if (pdev->instance->debug_flags & RADV_DEBUG_NO_DCC ||
if (instance->debug_flags & RADV_DEBUG_NO_DCC ||
(compression && compression->flags == VK_IMAGE_COMPRESSION_DISABLED_EXT)) {
return false;
}
@ -300,7 +303,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
}
/* DCC MSAA can't work on GFX10.3 and earlier without FMASK. */
if (pCreateInfo->samples > 1 && pdev->info.gfx_level < GFX11 && (pdev->instance->debug_flags & RADV_DEBUG_NO_FMASK))
if (pCreateInfo->samples > 1 && pdev->info.gfx_level < GFX11 && (instance->debug_flags & RADV_DEBUG_NO_FMASK))
return false;
return radv_are_formats_dcc_compatible(pdev, pCreateInfo->pNext, format, pCreateInfo->flags, sign_reinterpret);
@ -358,6 +361,7 @@ static inline bool
radv_use_fmask_for_image(const struct radv_device *device, const struct radv_image *image)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (pdev->info.gfx_level == GFX9 && image->vk.array_layers > 1) {
/* On GFX9, FMASK can be interleaved with layers and this isn't properly supported. */
@ -366,7 +370,7 @@ radv_use_fmask_for_image(const struct radv_device *device, const struct radv_ima
return pdev->use_fmask && image->vk.samples > 1 &&
((image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
(pdev->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
(instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
}
static inline bool
@ -374,12 +378,13 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima
const VkImageCreateInfo *pCreateInfo)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
const VkImageCompressionControlEXT *compression =
vk_find_struct_const(pCreateInfo->pNext, IMAGE_COMPRESSION_CONTROL_EXT);
if (pdev->instance->debug_flags & RADV_DEBUG_NO_HIZ ||
if (instance->debug_flags & RADV_DEBUG_NO_HIZ ||
(compression && compression->flags == VK_IMAGE_COMPRESSION_DISABLED_EXT))
return false;
@ -397,7 +402,7 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima
* allowed with VRS attachments because we need HTILE on GFX10.3.
*/
if (image->vk.extent.width * image->vk.extent.height < 8 * 8 &&
!(pdev->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS) &&
!(instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS) &&
!(gfx_level == GFX10_3 && device->vk.enabled_features.attachmentFragmentShadingRate))
return false;
@ -408,6 +413,7 @@ static bool
radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image *image)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* TC-compat CMASK is only available for GFX8+. */
if (pdev->info.gfx_level < GFX8)
@ -417,7 +423,7 @@ radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image
if (pdev->info.gfx_level == GFX9 && image->vk.samples > 2)
return false;
if (pdev->instance->debug_flags & RADV_DEBUG_NO_TC_COMPAT_CMASK)
if (instance->debug_flags & RADV_DEBUG_NO_TC_COMPAT_CMASK)
return false;
/* TC-compat CMASK with storage images is supported on GFX10+. */
@ -555,6 +561,7 @@ radv_patch_image_from_extra_info(struct radv_device *device, struct radv_image *
const struct radv_image_create_info *create_info, struct ac_surf_info *image_info)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkResult result = radv_patch_image_dimensions(device, image, create_info, image_info);
if (result != VK_SUCCESS)
@ -567,7 +574,7 @@ radv_patch_image_from_extra_info(struct radv_device *device, struct radv_image *
if (radv_surface_has_scanout(device, create_info)) {
image->planes[plane].surface.flags |= RADEON_SURF_SCANOUT;
if (pdev->instance->debug_flags & RADV_DEBUG_NO_DISPLAY_DCC)
if (instance->debug_flags & RADV_DEBUG_NO_DISPLAY_DCC)
image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC;
image_info->surf_index = NULL;
@ -760,6 +767,7 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image,
struct radeon_bo_metadata *md)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
static const VkComponentMapping fixedmapping;
const VkFormat plane_format = radv_image_get_plane_format(pdev, image, plane_id);
const unsigned plane_width = vk_format_get_plane_width(image->vk.format, plane_id, image->vk.extent.width);
@ -776,7 +784,7 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image,
false, desc, NULL);
ac_surface_compute_umd_metadata(&pdev->info, surface, image->vk.mip_levels, desc, &md->size_metadata, md->metadata,
pdev->instance->debug_flags & RADV_DEBUG_EXTRA_MD);
instance->debug_flags & RADV_DEBUG_EXTRA_MD);
}
void
@ -958,8 +966,9 @@ bool
radv_image_can_fast_clear(const struct radv_device *device, const struct radv_image *image)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (pdev->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
if (instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
return false;
if (vk_format_is_color(image->vk.format)) {
@ -1278,6 +1287,7 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
{
RADV_FROM_HANDLE(radv_device, device, _device);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
struct radv_image *image = NULL;
@ -1360,7 +1370,7 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
}
}
if (pdev->instance->debug_flags & RADV_DEBUG_IMG) {
if (instance->debug_flags & RADV_DEBUG_IMG) {
radv_image_print_info(device, image);
}
@ -1415,6 +1425,7 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r
unsigned queue_mask)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Don't compress exclusive images used on transfer queues when SDMA doesn't support HTILE.
* Note that HTILE is already disabled on concurrent images when not supported.
@ -1441,7 +1452,7 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r
* the number of decompressions from/to GENERAL.
*/
if (radv_image_is_tc_compat_htile(image) && queue_mask & (1u << RADV_QUEUE_GENERAL) &&
!pdev->instance->drirc.disable_tc_compat_htile_in_general) {
!instance->drirc.disable_tc_compat_htile_in_general) {
return true;
} else {
return false;

3
src/amd/vulkan/radv_image_view.c
View file

@ -415,6 +415,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag
uint32_t *fmask_state, VkImageCreateFlags img_create_flags)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const struct util_format_description *desc;
enum pipe_swizzle swizzle[4];
int first_non_void;
@ -505,7 +506,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag
if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && image->planes[0].surface.meta_offset) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
} else {
if (pdev->instance->drirc.disable_aniso_single_level) {
if (instance->drirc.disable_aniso_single_level) {
/* The last dword is unused by hw. The shader uses it to clear
* bits in the first dword of sampler state.
*/

151
src/amd/vulkan/radv_physical_device.c
View file

@ -56,27 +56,33 @@ typedef void *drmDevicePtr;
static bool
radv_perf_query_supported(const struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* SQTT / SPM interfere with the register states for perf counters, and
* the code has only been tested on GFX10.3 */
return pdev->info.gfx_level == GFX10_3 && !(pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP);
return pdev->info.gfx_level == GFX10_3 && !(instance->vk.trace_mode & RADV_TRACE_MODE_RGP);
}
static bool
radv_taskmesh_enabled(const struct radv_physical_device *pdev)
{
if (pdev->instance->debug_flags & RADV_DEBUG_NO_MESH_SHADER)
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (instance->debug_flags & RADV_DEBUG_NO_MESH_SHADER)
return false;
return pdev->use_ngg && !pdev->use_llvm && pdev->info.gfx_level >= GFX10_3 &&
!(pdev->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE) && pdev->info.has_gang_submit;
!(instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE) && pdev->info.has_gang_submit;
}
static bool
radv_transfer_queue_enabled(const struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Check if the GPU has SDMA support and transfer queues are allowed. */
if (pdev->info.sdma_ip_version == SDMA_UNKNOWN || !pdev->info.ip[AMD_IP_SDMA].num_queues ||
!(pdev->instance->perftest_flags & RADV_PERFTEST_TRANSFER_QUEUE))
!(instance->perftest_flags & RADV_PERFTEST_TRANSFER_QUEUE))
return false;
return pdev->info.gfx_level >= GFX9;
@ -85,7 +91,8 @@ radv_transfer_queue_enabled(const struct radv_physical_device *pdev)
static bool
radv_vrs_attachment_enabled(const struct radv_physical_device *pdev)
{
return pdev->info.gfx_level >= GFX11 || !(pdev->instance->debug_flags & RADV_DEBUG_NO_HIZ);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return pdev->info.gfx_level >= GFX11 || !(instance->debug_flags & RADV_DEBUG_NO_HIZ);
}
static bool
@ -97,7 +104,8 @@ radv_calibrated_timestamps_enabled(const struct radv_physical_device *pdev)
static bool
radv_shader_object_enabled(const struct radv_physical_device *pdev)
{
return !pdev->use_llvm && pdev->instance->perftest_flags & RADV_PERFTEST_SHADER_OBJECT;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return !pdev->use_llvm && instance->perftest_flags & RADV_PERFTEST_SHADER_OBJECT;
}
bool
@ -115,7 +123,8 @@ radv_enable_rt(const struct radv_physical_device *pdev, bool rt_pipelines)
bool
radv_emulate_rt(const struct radv_physical_device *pdev)
{
return pdev->instance->perftest_flags & RADV_PERFTEST_EMULATE_RT;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return instance->perftest_flags & RADV_PERFTEST_EMULATE_RT;
}
static bool
@ -139,31 +148,32 @@ parse_hex(char *out, const char *in, unsigned length)
static void
radv_physical_device_init_cache_key(struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_physical_device_cache_key *key = &pdev->cache_key;
key->family = pdev->info.family;
key->ptr_size = sizeof(void *);
key->conformant_trunc_coord = pdev->info.conformant_trunc_coord;
key->clear_lds = pdev->instance->drirc.clear_lds;
key->clear_lds = instance->drirc.clear_lds;
key->cs_wave32 = pdev->cs_wave_size == 32;
key->disable_aniso_single_level = pdev->instance->drirc.disable_aniso_single_level && pdev->info.gfx_level < GFX8;
key->disable_shrink_image_store = pdev->instance->drirc.disable_shrink_image_store;
key->disable_sinking_load_input_fs = pdev->instance->drirc.disable_sinking_load_input_fs;
key->dual_color_blend_by_location = pdev->instance->drirc.dual_color_blend_by_location;
key->emulate_rt = !!(pdev->instance->perftest_flags & RADV_PERFTEST_EMULATE_RT);
key->disable_aniso_single_level = instance->drirc.disable_aniso_single_level && pdev->info.gfx_level < GFX8;
key->disable_shrink_image_store = instance->drirc.disable_shrink_image_store;
key->disable_sinking_load_input_fs = instance->drirc.disable_sinking_load_input_fs;
key->dual_color_blend_by_location = instance->drirc.dual_color_blend_by_location;
key->emulate_rt = !!(instance->perftest_flags & RADV_PERFTEST_EMULATE_RT);
key->ge_wave32 = pdev->ge_wave_size == 32;
key->invariant_geom = !!(pdev->instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM);
key->lower_discard_to_demote = !!(pdev->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE);
key->invariant_geom = !!(instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM);
key->lower_discard_to_demote = !!(instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE);
key->mesh_fast_launch_2 = pdev->mesh_fast_launch_2;
key->no_fmask = !!(pdev->instance->debug_flags & RADV_DEBUG_NO_FMASK);
key->no_ngg_gs = !!(pdev->instance->debug_flags & RADV_DEBUG_NO_NGG_GS);
key->no_rt = !!(pdev->instance->debug_flags & RADV_DEBUG_NO_RT);
key->no_fmask = !!(instance->debug_flags & RADV_DEBUG_NO_FMASK);
key->no_ngg_gs = !!(instance->debug_flags & RADV_DEBUG_NO_NGG_GS);
key->no_rt = !!(instance->debug_flags & RADV_DEBUG_NO_RT);
key->ps_wave32 = pdev->ps_wave_size == 32;
key->rt_wave64 = pdev->rt_wave_size == 64;
key->split_fma = !!(pdev->instance->debug_flags & RADV_DEBUG_SPLIT_FMA);
key->ssbo_non_uniform = pdev->instance->drirc.ssbo_non_uniform;
key->tex_non_uniform = pdev->instance->drirc.tex_non_uniform;
key->split_fma = !!(instance->debug_flags & RADV_DEBUG_SPLIT_FMA);
key->ssbo_non_uniform = instance->drirc.ssbo_non_uniform;
key->tex_non_uniform = instance->drirc.tex_non_uniform;
key->use_llvm = pdev->use_llvm;
key->use_ngg = pdev->use_ngg;
key->use_ngg_culling = pdev->use_ngg_culling;
@ -217,6 +227,7 @@ radv_get_device_uuid(const struct radeon_info *gpu_info, void *uuid)
static void
radv_physical_device_init_queue_table(struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
int idx = 0;
pdev->vk_queue_to_radv[idx] = RADV_QUEUE_GENERAL;
idx++;
@ -224,12 +235,12 @@ radv_physical_device_init_queue_table(struct radv_physical_device *pdev)
for (unsigned i = 1; i < RADV_MAX_QUEUE_FAMILIES; i++)
pdev->vk_queue_to_radv[i] = RADV_MAX_QUEUE_FAMILIES + 1;
if (pdev->info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdev->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
if (pdev->info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
pdev->vk_queue_to_radv[idx] = RADV_QUEUE_COMPUTE;
idx++;
}
if (pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (pdev->info.ip[pdev->vid_decode_ip].num_queues > 0) {
pdev->vk_queue_to_radv[idx] = RADV_QUEUE_VIDEO_DEC;
idx++;
@ -259,7 +270,8 @@ enum radv_heap {
static uint64_t
radv_get_adjusted_vram_size(struct radv_physical_device *pdev)
{
int ov = pdev->instance->drirc.override_vram_size;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
int ov = instance->drirc.override_vram_size;
if (ov >= 0)
return MIN2((uint64_t)pdev->info.vram_size_kb * 1024, (uint64_t)ov << 20);
return (uint64_t)pdev->info.vram_size_kb * 1024;
@ -281,6 +293,7 @@ radv_get_vram_size(struct radv_physical_device *pdev)
static void
radv_physical_device_init_mem_types(struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint64_t visible_vram_size = radv_get_visible_vram_size(pdev);
uint64_t vram_size = radv_get_vram_size(pdev);
uint64_t gtt_size = (uint64_t)pdev->info.gart_size_kb * 1024;
@ -292,7 +305,7 @@ radv_physical_device_init_mem_types(struct radv_physical_device *pdev)
if (!pdev->info.has_dedicated_vram) {
const uint64_t total_size = gtt_size + visible_vram_size;
if (pdev->instance->drirc.enable_unified_heap_on_apu) {
if (instance->drirc.enable_unified_heap_on_apu) {
/* Some applications seem better when the driver exposes only one heap of VRAM on APUs. */
visible_vram_size = total_size;
gtt_size = 0;
@ -459,6 +472,7 @@ static void
radv_physical_device_get_supported_extensions(const struct radv_physical_device *pdev,
struct vk_device_extension_table *out_ext)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const struct vk_device_extension_table ext = {
.KHR_8bit_storage = true,
.KHR_16bit_storage = true,
@ -512,10 +526,10 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
* but the feature is useful enough to hide behind an opt-in mechanism for now.
* If the instance only enables surface extensions that unconditionally support present wait,
* we can also expose the extension that way. */
.KHR_present_id = pdev->instance->drirc.enable_khr_present_wait ||
wsi_common_vk_instance_supports_present_wait(&pdev->instance->vk),
.KHR_present_wait = pdev->instance->drirc.enable_khr_present_wait ||
wsi_common_vk_instance_supports_present_wait(&pdev->instance->vk),
.KHR_present_id =
instance->drirc.enable_khr_present_wait || wsi_common_vk_instance_supports_present_wait(&instance->vk),
.KHR_present_wait =
instance->drirc.enable_khr_present_wait || wsi_common_vk_instance_supports_present_wait(&instance->vk),
.KHR_push_descriptor = true,
.KHR_ray_query = radv_enable_rt(pdev, false),
.KHR_ray_tracing_maintenance1 = radv_enable_rt(pdev, false),
@ -550,12 +564,12 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
.KHR_uniform_buffer_standard_layout = true,
.KHR_variable_pointers = true,
.KHR_vertex_attribute_divisor = true,
.KHR_video_queue = !!(pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_video_queue = !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_video_decode_av1 = (pdev->info.vcn_ip_version >= VCN_3_0_0 && pdev->info.vcn_ip_version != VCN_3_0_33 &&
VIDEO_CODEC_AV1DEC && !!(pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE)),
.KHR_video_decode_queue = !!(pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_video_decode_h264 = VIDEO_CODEC_H264DEC && !!(pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_video_decode_h265 = VIDEO_CODEC_H265DEC && !!(pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
VIDEO_CODEC_AV1DEC && !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE)),
.KHR_video_decode_queue = !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_video_decode_h264 = VIDEO_CODEC_H264DEC && !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_video_decode_h265 = VIDEO_CODEC_H265DEC && !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE),
.KHR_vulkan_memory_model = true,
.KHR_workgroup_memory_explicit_layout = true,
.KHR_zero_initialize_workgroup_memory = true,
@ -569,7 +583,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
.EXT_conditional_rendering = true,
.EXT_conservative_rasterization = pdev->info.gfx_level >= GFX9,
.EXT_custom_border_color = true,
.EXT_debug_marker = pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP,
.EXT_debug_marker = instance->vk.trace_mode & RADV_TRACE_MODE_RGP,
.EXT_depth_bias_control = true,
.EXT_depth_clamp_zero_one = true,
.EXT_depth_clip_control = true,
@ -592,7 +606,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
.EXT_fragment_shader_interlock = radv_has_pops(pdev),
.EXT_global_priority = true,
.EXT_global_priority_query = true,
.EXT_graphics_pipeline_library = !pdev->use_llvm && !(pdev->instance->debug_flags & RADV_DEBUG_NO_GPL),
.EXT_graphics_pipeline_library = !pdev->use_llvm && !(instance->debug_flags & RADV_DEBUG_NO_GPL),
.EXT_host_query_reset = true,
.EXT_image_2d_view_of_3d = true,
.EXT_image_compression_control = true,
@ -648,7 +662,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
.EXT_tooling_info = true,
.EXT_transform_feedback = true,
.EXT_vertex_attribute_divisor = true,
.EXT_vertex_input_dynamic_state = !pdev->use_llvm && !pdev->instance->drirc.enable_dgc,
.EXT_vertex_input_dynamic_state = !pdev->use_llvm && !instance->drirc.enable_dgc,
.EXT_ycbcr_image_arrays = true,
.AMD_buffer_marker = true,
.AMD_device_coherent_memory = true,
@ -677,8 +691,8 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
.GOOGLE_user_type = true,
.INTEL_shader_integer_functions2 = true,
.NV_compute_shader_derivatives = true,
.NV_device_generated_commands = !pdev->use_llvm && pdev->instance->drirc.enable_dgc,
.NV_device_generated_commands_compute = !pdev->use_llvm && pdev->instance->drirc.enable_dgc,
.NV_device_generated_commands = !pdev->use_llvm && instance->drirc.enable_dgc,
.NV_device_generated_commands_compute = !pdev->use_llvm && instance->drirc.enable_dgc,
/* Undocumented extension purely for vkd3d-proton. This check is to prevent anyone else from
* using it.
*/
@ -692,6 +706,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
static void
radv_physical_device_get_features(const struct radv_physical_device *pdev, struct vk_features *features)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
bool taskmesh_en = radv_taskmesh_enabled(pdev);
bool has_perf_query = radv_perf_query_supported(pdev);
bool has_shader_image_float_minmax =
@ -1155,7 +1170,7 @@ radv_physical_device_get_features(const struct radv_physical_device *pdev, struc
/* VK_EXT_device_fault */
.deviceFault = true,
.deviceFaultVendorBinary = pdev->instance->debug_flags & RADV_DEBUG_HANG,
.deviceFaultVendorBinary = instance->debug_flags & RADV_DEBUG_HANG,
/* VK_EXT_depth_clamp_zero_one */
.depthClampZeroOne = true,
@ -1199,7 +1214,8 @@ radv_max_descriptor_set_size()
static uint32_t
radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdev)
{
uint32_t uniform_offset_alignment = pdev->instance->drirc.override_uniform_offset_alignment;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint32_t uniform_offset_alignment = instance->drirc.override_uniform_offset_alignment;
if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
fprintf(stderr,
"ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
@ -1215,12 +1231,14 @@ radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdev)
static const char *
radv_get_compiler_string(struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (!pdev->use_llvm) {
/* Some games like SotTR apply shader workarounds if the LLVM
* version is too old or if the LLVM version string is
* missing. This gives 2-5% performance with SotTR and ACO.
*/
if (pdev->instance->drirc.report_llvm9_version_string) {
if (instance->drirc.report_llvm9_version_string) {
return " (LLVM 9.0.1)";
}
@ -1928,8 +1946,6 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
goto fail_alloc;
}
pdev->instance = instance;
#ifdef _WIN32
pdev->ws = radv_null_winsys_create();
#else
@ -2000,25 +2016,25 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
radv_get_driver_uuid(&pdev->driver_uuid);
radv_get_device_uuid(&pdev->info, &pdev->device_uuid);
pdev->dcc_msaa_allowed = (pdev->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
pdev->dcc_msaa_allowed = (instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
pdev->use_fmask = pdev->info.gfx_level < GFX11 && !(pdev->instance->debug_flags & RADV_DEBUG_NO_FMASK);
pdev->use_fmask = pdev->info.gfx_level < GFX11 && !(instance->debug_flags & RADV_DEBUG_NO_FMASK);
pdev->use_ngg = (pdev->info.gfx_level >= GFX10 && pdev->info.family != CHIP_NAVI14 &&
!(pdev->instance->debug_flags & RADV_DEBUG_NO_NGG)) ||
!(instance->debug_flags & RADV_DEBUG_NO_NGG)) ||
pdev->info.gfx_level >= GFX11;
/* TODO: Investigate if NGG culling helps on GFX11. */
pdev->use_ngg_culling = pdev->use_ngg && pdev->info.max_render_backends > 1 &&
(pdev->info.gfx_level == GFX10_3 || (pdev->instance->perftest_flags & RADV_PERFTEST_NGGC)) &&
!(pdev->instance->debug_flags & RADV_DEBUG_NO_NGGC);
(pdev->info.gfx_level == GFX10_3 || (instance->perftest_flags & RADV_PERFTEST_NGGC)) &&
!(instance->debug_flags & RADV_DEBUG_NO_NGGC);
pdev->use_ngg_streamout = pdev->info.gfx_level >= GFX11;
pdev->emulate_ngg_gs_query_pipeline_stat = pdev->use_ngg && pdev->info.gfx_level < GFX11;
pdev->mesh_fast_launch_2 =
pdev->info.gfx_level >= GFX11 && !(pdev->instance->debug_flags & RADV_DEBUG_NO_GS_FAST_LAUNCH_2);
pdev->info.gfx_level >= GFX11 && !(instance->debug_flags & RADV_DEBUG_NO_GS_FAST_LAUNCH_2);
pdev->emulate_mesh_shader_queries = pdev->info.gfx_level == GFX10_3;
@ -2029,14 +2045,14 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
pdev->rt_wave_size = 64;
if (pdev->info.gfx_level >= GFX10) {
if (pdev->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
if (instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
pdev->cs_wave_size = 32;
/* For pixel shaders, wave64 is recommended. */
if (pdev->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
if (instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
pdev->ps_wave_size = 32;
if (pdev->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
if (instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
pdev->ge_wave_size = 32;
/* Default to 32 on RDNA1-2 as that gives better perf due to less issues with divergence.
@ -2044,10 +2060,10 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
* wave32 VOPD for VALU dependent code.
* (as well as the SALU count becoming more problematic with wave32)
*/
if (pdev->instance->perftest_flags & RADV_PERFTEST_RT_WAVE_32 || pdev->info.gfx_level < GFX11)
if (instance->perftest_flags & RADV_PERFTEST_RT_WAVE_32 || pdev->info.gfx_level < GFX11)
pdev->rt_wave_size = 32;
if (pdev->instance->perftest_flags & RADV_PERFTEST_RT_WAVE_64 || pdev->instance->drirc.force_rt_wave64)
if (instance->perftest_flags & RADV_PERFTEST_RT_WAVE_64 || instance->drirc.force_rt_wave64)
pdev->rt_wave_size = 64;
}
@ -2101,7 +2117,7 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
radv_get_physical_device_properties(pdev);
if ((pdev->instance->debug_flags & RADV_DEBUG_INFO))
if ((instance->debug_flags & RADV_DEBUG_INFO))
ac_print_gpu_info(&pdev->info, stdout);
radv_init_physical_device_decoder(pdev);
@ -2181,6 +2197,7 @@ void
radv_physical_device_destroy(struct vk_physical_device *vk_device)
{
struct radv_physical_device *pdev = container_of(vk_device, struct radv_physical_device, vk);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
radv_finish_wsi(pdev);
ac_destroy_perfcounters(&pdev->ac_perfcounters);
@ -2191,19 +2208,20 @@ radv_physical_device_destroy(struct vk_physical_device *vk_device)
if (pdev->master_fd != -1)
close(pdev->master_fd);
vk_physical_device_finish(&pdev->vk);
vk_free(&pdev->instance->vk.alloc, pdev);
vk_free(&instance->vk.alloc, pdev);
}
static void
radv_get_physical_device_queue_family_properties(struct radv_physical_device *pdev, uint32_t *pCount,
VkQueueFamilyProperties **pQueueFamilyProperties)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
int num_queue_families = 1;
int idx;
if (pdev->info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdev->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
if (pdev->info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
num_queue_families++;
if (pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (pdev->info.ip[pdev->vid_decode_ip].num_queues > 0)
num_queue_families++;
}
@ -2238,7 +2256,7 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd
idx++;
}
if (pdev->info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdev->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
if (pdev->info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
VkQueueFlags compute_flags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT;
if (!radv_sparse_queue_enabled(pdev))
compute_flags |= VK_QUEUE_SPARSE_BINDING_BIT;
@ -2253,7 +2271,7 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd
}
}
if (pdev->instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (instance->perftest_flags & RADV_PERFTEST_VIDEO_DECODE) {
if (pdev->info.ip[pdev->vid_decode_ip].num_queues > 0) {
if (*pCount > idx) {
*pQueueFamilyProperties[idx] = (VkQueueFamilyProperties){
@ -2359,6 +2377,7 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
{
RADV_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkPhysicalDeviceMemoryProperties *memory_properties = &pdev->memory_properties;
/* For all memory heaps, the computation of budget is as follow:
@ -2371,7 +2390,7 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
* in presence of shared buffers).
*/
if (!pdev->info.has_dedicated_vram) {
if (pdev->instance->drirc.enable_unified_heap_on_apu) {
if (instance->drirc.enable_unified_heap_on_apu) {
/* When the heaps are unified, only the visible VRAM heap is exposed on APUs. */
assert(pdev->heaps == RADV_HEAP_VRAM_VIS);
assert(pdev->memory_properties.memoryHeaps[0].flags == VK_MEMORY_HEAP_DEVICE_LOCAL_BIT);
@ -2576,23 +2595,23 @@ radv_GetPhysicalDeviceToolProperties(VkPhysicalDevice physicalDevice, uint32_t *
VkPhysicalDeviceToolProperties *pToolProperties)
{
VK_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VK_OUTARRAY_MAKE_TYPED(VkPhysicalDeviceToolProperties, out, pToolProperties, pToolCount);
bool rgp_enabled, rmv_enabled, rra_enabled;
uint32_t tool_count = 0;
/* RGP */
rgp_enabled = pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP;
rgp_enabled = instance->vk.trace_mode & RADV_TRACE_MODE_RGP;
if (rgp_enabled)
tool_count++;
/* RMV */
rmv_enabled = pdev->instance->vk.trace_mode & VK_TRACE_MODE_RMV;
rmv_enabled = instance->vk.trace_mode & VK_TRACE_MODE_RMV;
if (rmv_enabled)
tool_count++;
/* RRA */
rra_enabled = pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RRA;
rra_enabled = instance->vk.trace_mode & RADV_TRACE_MODE_RRA;
if (rra_enabled)
tool_count++;

22
src/amd/vulkan/radv_pipeline.c
View file

@ -64,16 +64,20 @@ bool
radv_pipeline_capture_shaders(const struct radv_device *device, VkPipelineCreateFlags2KHR flags)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return (flags & VK_PIPELINE_CREATE_2_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) ||
(pdev->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS) || device->keep_shader_info;
(instance->debug_flags & RADV_DEBUG_DUMP_SHADERS) || device->keep_shader_info;
}
bool
radv_pipeline_capture_shader_stats(const struct radv_device *device, VkPipelineCreateFlags2KHR flags)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return (flags & VK_PIPELINE_CREATE_2_CAPTURE_STATISTICS_BIT_KHR) ||
(pdev->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) || device->keep_shader_info;
(instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) || device->keep_shader_info;
}
void
@ -150,6 +154,7 @@ radv_pipeline_get_shader_key(const struct radv_device *device, const VkPipelineS
VkPipelineCreateFlags2KHR flags, const void *pNext)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
struct radv_shader_stage_key key = {0};
@ -159,12 +164,12 @@ radv_pipeline_get_shader_key(const struct radv_device *device, const VkPipelineS
key.optimisations_disabled = 1;
if (stage->stage & RADV_GRAPHICS_STAGE_BITS) {
key.version = pdev->instance->drirc.override_graphics_shader_version;
key.version = instance->drirc.override_graphics_shader_version;
} else if (stage->stage & RADV_RT_STAGE_BITS) {
key.version = pdev->instance->drirc.override_ray_tracing_shader_version;
key.version = instance->drirc.override_ray_tracing_shader_version;
} else {
assert(stage->stage == VK_SHADER_STAGE_COMPUTE_BIT);
key.version = pdev->instance->drirc.override_compute_shader_version;
key.version = instance->drirc.override_compute_shader_version;
}
const VkPipelineRobustnessCreateInfoEXT *pipeline_robust_info =
@ -467,6 +472,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
struct radv_shader_stage *stage)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
enum amd_gfx_level gfx_level = pdev->info.gfx_level;
bool progress;
@ -528,7 +534,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
NIR_PASS(progress, stage->nir, nir_opt_load_store_vectorize, &vectorize_opts);
if (progress) {
NIR_PASS(_, stage->nir, nir_copy_prop);
NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !pdev->instance->drirc.disable_shrink_image_store);
NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !instance->drirc.disable_shrink_image_store);
/* Gather info again, to update whether 8/16-bit are used. */
nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir));
@ -740,9 +746,11 @@ bool
radv_shader_should_clear_lds(const struct radv_device *device, const nir_shader *shader)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return (shader->info.stage == MESA_SHADER_COMPUTE || shader->info.stage == MESA_SHADER_MESH ||
shader->info.stage == MESA_SHADER_TASK) &&
shader->info.shared_size > 0 && pdev->instance->drirc.clear_lds;
shader->info.shared_size > 0 && instance->drirc.clear_lds;
}
static uint32_t

3
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -39,6 +39,7 @@ static bool
radv_is_cache_disabled(struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* The buffer address used for debug printf is hardcoded. */
if (device->printf.buffer_addr)
@ -47,7 +48,7 @@ radv_is_cache_disabled(struct radv_device *device)
/* Pipeline caches can be disabled with RADV_DEBUG=nocache, with MESA_GLSL_CACHE_DISABLE=1 and
* when ACO_DEBUG is used. MESA_GLSL_CACHE_DISABLE is done elsewhere.
*/
return (pdev->instance->debug_flags & RADV_DEBUG_NO_CACHE) || (pdev->use_llvm ? 0 : aco_get_codegen_flags());
return (instance->debug_flags & RADV_DEBUG_NO_CACHE) || (pdev->use_llvm ? 0 : aco_get_codegen_flags());
}
void

17
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -1690,6 +1690,7 @@ struct radv_ps_epilog_key
radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_ps_epilog_state *state)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
unsigned col_format = 0, is_int8 = 0, is_int10 = 0, is_float32 = 0, z_format = 0;
struct radv_ps_epilog_key key;
@ -1737,7 +1738,7 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_
key.spi_shader_col_format = col_format;
key.color_is_int8 = pdev->info.gfx_level < GFX8 ? is_int8 : 0;
key.color_is_int10 = pdev->info.gfx_level < GFX8 ? is_int10 : 0;
key.enable_mrt_output_nan_fixup = pdev->instance->drirc.enable_mrt_output_nan_fixup ? is_float32 : 0;
key.enable_mrt_output_nan_fixup = instance->drirc.enable_mrt_output_nan_fixup ? is_float32 : 0;
key.colors_written = state->colors_written;
key.mrt0_is_dual_src = state->mrt0_is_dual_src;
key.export_depth = state->export_depth;
@ -1999,6 +2000,7 @@ radv_fill_shader_info_ngg(struct radv_device *device, struct radv_shader_stage *
VkShaderStageFlagBits active_nir_stages)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (!pdev->cache_key.use_ngg)
return;
@ -2037,7 +2039,7 @@ radv_fill_shader_info_ngg(struct radv_device *device, struct radv_shader_stage *
}
if ((last_vgt_stage && last_vgt_stage->nir->xfb_info) ||
((pdev->instance->debug_flags & RADV_DEBUG_NO_NGG_GS) && stages[MESA_SHADER_GEOMETRY].nir)) {
((instance->debug_flags & RADV_DEBUG_NO_NGG_GS) && stages[MESA_SHADER_GEOMETRY].nir)) {
/* NGG needs to be disabled on GFX10/GFX10.3 when:
* - streamout is used because NGG streamout isn't supported
* - NGG GS is explictly disabled to workaround performance issues
@ -2500,7 +2502,8 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
struct radv_shader **gs_copy_shader, struct radv_shader_binary **gs_copy_binary)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const bool nir_cache = pdev->instance->perftest_flags & RADV_PERFTEST_NIR_CACHE;
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const bool nir_cache = instance->perftest_flags & RADV_PERFTEST_NIR_CACHE;
for (unsigned s = 0; s < MESA_VULKAN_SHADER_STAGES; s++) {
if (!stages[s].entrypoint)
continue;
@ -2512,7 +2515,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
struct radv_spirv_to_nir_options options = {
.lower_view_index_to_zero = !gfx_state->has_multiview_view_index,
.fix_dual_src_mrt1_export =
gfx_state->ps.epilog.mrt0_is_dual_src && pdev->instance->drirc.dual_color_blend_by_location,
gfx_state->ps.epilog.mrt0_is_dual_src && instance->drirc.dual_color_blend_by_location,
};
blake3_hash key;
@ -2664,13 +2667,14 @@ radv_should_compute_pipeline_hash(const struct radv_device *device, const struct
bool fast_linking_enabled)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Skip computing the pipeline hash when GPL fast-linking is enabled because these shaders aren't
* supposed to be cached and computing the hash is costly. Though, make sure it's always computed
* when RGP is enabled, otherwise ISA isn't reported.
*/
return !fast_linking_enabled ||
((pdev->instance->vk.trace_mode & RADV_TRACE_MODE_RGP) && pipeline->base.type == RADV_PIPELINE_GRAPHICS);
((instance->vk.trace_mode & RADV_TRACE_MODE_RGP) && pipeline->base.type == RADV_PIPELINE_GRAPHICS);
}
static VkResult
@ -3729,12 +3733,13 @@ static bool
gfx103_pipeline_vrs_coarse_shading(const struct radv_device *device, const struct radv_graphics_pipeline *pipeline)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
if (pdev->info.gfx_level != GFX10_3)
return false;
if (pdev->instance->debug_flags & RADV_DEBUG_NO_VRS_FLAT_SHADING)
if (instance->debug_flags & RADV_DEBUG_NO_VRS_FLAT_SHADING)
return false;
if (ps && !ps->info.ps.allow_flat_shading)

12
src/amd/vulkan/radv_private.h
View file

@ -267,8 +267,6 @@ struct radv_physical_device_cache_key {
struct radv_physical_device {
struct vk_physical_device vk;
struct radv_instance *instance;
struct radeon_winsys *ws;
struct radeon_info info;
char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
@ -372,6 +370,12 @@ struct radv_physical_device {
struct radv_physical_device_cache_key cache_key;
};
static inline struct radv_instance *
radv_physical_device_instance(const struct radv_physical_device *pdev)
{
return (struct radv_instance *)pdev->vk.instance;
}
uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
VkResult create_null_physical_device(struct vk_instance *vk_instance);
@ -746,9 +750,11 @@ struct radv_meta_state {
static inline bool
radv_sparse_queue_enabled(const struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Dedicated sparse queue requires VK_QUEUE_SUBMIT_MODE_THREADED, which is incompatible with
* VK_DEVICE_TIMELINE_MODE_EMULATED. */
return pdev->info.has_timeline_syncobj && !pdev->instance->drirc.legacy_sparse_binding;
return pdev->info.has_timeline_syncobj && !instance->drirc.legacy_sparse_binding;
}
static inline enum radv_queue_family

8
src/amd/vulkan/radv_query.c
View file

@ -1736,6 +1736,7 @@ radv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPoo
RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(pool->bo);
uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
@ -1751,7 +1752,7 @@ radv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPoo
/* Workaround engines that forget to properly specify WAIT_BIT because some driver implicitly
* synchronizes before query copy.
*/
if (pdev->instance->drirc.flush_before_query_copy)
if (instance->drirc.flush_before_query_copy)
cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
/* From the Vulkan spec 1.1.108:
@ -2599,6 +2600,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
const unsigned num_queries = MAX2(util_bitcount(cmd_buffer->state.render.view_mask), 1);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
const uint64_t va = radv_buffer_get_va(pool->bo);
@ -2607,7 +2609,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta
radv_cs_add_buffer(device->ws, cs, pool->bo);
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
if (pdev->instance->drirc.flush_before_timestamp_write) {
if (instance->drirc.flush_before_timestamp_write) {
radeon_check_space(device->ws, cmd_buffer->cs, 1);
radeon_emit(cmd_buffer->cs, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
}
@ -2621,7 +2623,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta
return;
}
if (pdev->instance->drirc.flush_before_timestamp_write) {
if (instance->drirc.flush_before_timestamp_write) {
/* Make sure previously launched waves have finished */
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
}

5
src/amd/vulkan/radv_sampler.c
View file

@ -197,6 +197,7 @@ static void
radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, const VkSamplerCreateInfo *pCreateInfo)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
bool compat_mode = pdev->info.gfx_level == GFX8 || pdev->info.gfx_level == GFX9;
@ -248,12 +249,12 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, cons
if (pdev->info.gfx_level >= GFX10) {
sampler->state[2] |= S_008F38_LOD_BIAS(radv_float_to_sfixed(CLAMP(pCreateInfo->mipLodBias, -32, 31), 8)) |
S_008F38_ANISO_OVERRIDE_GFX10(pdev->instance->drirc.disable_aniso_single_level);
S_008F38_ANISO_OVERRIDE_GFX10(instance->drirc.disable_aniso_single_level);
} else {
sampler->state[2] |=
S_008F38_LOD_BIAS(radv_float_to_sfixed(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
S_008F38_DISABLE_LSB_CEIL(pdev->info.gfx_level <= GFX8) | S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE_GFX8(pdev->instance->drirc.disable_aniso_single_level && pdev->info.gfx_level >= GFX8);
S_008F38_ANISO_OVERRIDE_GFX8(instance->drirc.disable_aniso_single_level && pdev->info.gfx_level >= GFX8);
}
if (pdev->info.gfx_level >= GFX11) {

44
src/amd/vulkan/radv_shader.c
View file

@ -64,9 +64,10 @@
static void
get_nir_options_for_stage(struct radv_physical_device *pdev, gl_shader_stage stage)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
nir_shader_compiler_options *options = &pdev->nir_options[stage];
bool split_fma = (stage <= MESA_SHADER_GEOMETRY || stage == MESA_SHADER_MESH) &&
pdev->instance->debug_flags & RADV_DEBUG_SPLIT_FMA;
bool split_fma =
(stage <= MESA_SHADER_GEOMETRY || stage == MESA_SHADER_MESH) && instance->debug_flags & RADV_DEBUG_SPLIT_FMA;
ac_set_nir_options(&pdev->info, pdev->use_llvm, options);
@ -109,11 +110,12 @@ bool
radv_can_dump_shader(struct radv_device *device, nir_shader *nir, bool meta_shader)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (!(pdev->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
if (!(instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
return false;
if ((is_meta_shader(nir) || meta_shader) && !(pdev->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS))
if ((is_meta_shader(nir) || meta_shader) && !(instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS))
return false;
return true;
@ -123,9 +125,10 @@ bool
radv_can_dump_shader_stats(struct radv_device *device, nir_shader *nir)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Only dump non-meta shader stats. */
return pdev->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS && !is_meta_shader(nir);
return instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS && !is_meta_shader(nir);
}
void
@ -256,7 +259,7 @@ radv_spirv_nir_debug(void *private_data, enum nir_spirv_debug_level level, size_
{
struct radv_shader_debug_data *debug_data = private_data;
const struct radv_physical_device *pdev = radv_device_physical(debug_data->device);
struct radv_instance *instance = pdev->instance;
struct radv_instance *instance = radv_physical_device_instance(pdev);
static const VkDebugReportFlagsEXT vk_flags[] = {
[NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
@ -275,7 +278,7 @@ radv_compiler_debug(void *private_data, enum aco_compiler_debug_level level, con
{
struct radv_shader_debug_data *debug_data = private_data;
const struct radv_physical_device *pdev = radv_device_physical(debug_data->device);
struct radv_instance *instance = pdev->instance;
struct radv_instance *instance = radv_physical_device_instance(pdev);
static const VkDebugReportFlagsEXT vk_flags[] = {
[ACO_COMPILER_DEBUG_LEVEL_PERFWARN] = VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT,
@ -311,6 +314,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
const struct radv_spirv_to_nir_options *options, bool is_internal)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
unsigned subgroup_size = 64, ballot_bit_size = 64;
const unsigned required_subgroup_size = stage->key.subgroup_required_size * 32;
if (required_subgroup_size) {
@ -337,8 +341,8 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
uint32_t *spirv = (uint32_t *)stage->spirv.data;
assert(stage->spirv.size % 4 == 0);
bool dump_meta = pdev->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS;
if ((pdev->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV) && (!is_internal || dump_meta))
bool dump_meta = instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS;
if ((instance->debug_flags & RADV_DEBUG_DUMP_SPIRV) && (!is_internal || dump_meta))
radv_print_spirv(stage->spirv.data, stage->spirv.size, stderr);
uint32_t num_spec_entries = 0;
@ -632,7 +636,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
});
NIR_PASS(_, nir, nir_lower_load_const_to_scalar);
NIR_PASS(_, nir, nir_opt_shrink_stores, !pdev->instance->drirc.disable_shrink_image_store);
NIR_PASS(_, nir, nir_opt_shrink_stores, !instance->drirc.disable_shrink_image_store);
if (!stage->key.optimisations_disabled)
radv_optimize_nir(nir, false);
@ -2437,16 +2441,17 @@ radv_fill_nir_compiler_options(struct radv_nir_compiler_options *options, struct
bool keep_statistic_info)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* robust_buffer_access_llvm here used by LLVM only, pipeline robustness is not exposed there. */
options->robust_buffer_access_llvm = device->buffer_robustness >= RADV_BUFFER_ROBUSTNESS_1;
options->wgp_mode = should_use_wgp;
options->info = &pdev->info;
options->dump_shader = can_dump_shader;
options->dump_preoptir = options->dump_shader && pdev->instance->debug_flags & RADV_DEBUG_PREOPTIR;
options->dump_preoptir = options->dump_shader && instance->debug_flags & RADV_DEBUG_PREOPTIR;
options->record_ir = keep_shader_info;
options->record_stats = keep_statistic_info;
options->check_ir = pdev->instance->debug_flags & RADV_DEBUG_CHECKIR;
options->check_ir = instance->debug_flags & RADV_DEBUG_CHECKIR;
options->enable_mrt_output_nan_fixup = gfx_state ? gfx_state->ps.epilog.enable_mrt_output_nan_fixup : false;
}
@ -2623,12 +2628,13 @@ struct radv_shader *
radv_create_rt_prolog(struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_shader *prolog;
struct radv_shader_args in_args = {0};
struct radv_shader_args out_args = {0};
struct radv_nir_compiler_options options = {0};
radv_fill_nir_compiler_options(&options, device, NULL, false, pdev->instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS,
false, radv_device_fault_detection_enabled(device), false);
radv_fill_nir_compiler_options(&options, device, NULL, false, instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS, false,
radv_device_fault_detection_enabled(device), false);
struct radv_shader_info info = {0};
info.stage = MESA_SHADER_COMPUTE;
info.loads_push_constants = true;
@ -2688,11 +2694,12 @@ struct radv_shader_part *
radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_key *key)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_shader_part *prolog;
struct radv_shader_args args = {0};
struct radv_nir_compiler_options options = {0};
radv_fill_nir_compiler_options(&options, device, NULL, false, pdev->instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS,
false, radv_device_fault_detection_enabled(device), false);
radv_fill_nir_compiler_options(&options, device, NULL, false, instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS, false,
radv_device_fault_detection_enabled(device), false);
struct radv_shader_info info = {0};
info.stage = MESA_SHADER_VERTEX;
@ -2755,11 +2762,12 @@ radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_ke
struct radv_shader_part_binary **binary_out)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_shader_part *epilog;
struct radv_shader_args args = {0};
struct radv_nir_compiler_options options = {0};
radv_fill_nir_compiler_options(&options, device, NULL, false, pdev->instance->debug_flags & RADV_DEBUG_DUMP_EPILOGS,
false, radv_device_fault_detection_enabled(device), false);
radv_fill_nir_compiler_options(&options, device, NULL, false, instance->debug_flags & RADV_DEBUG_DUMP_EPILOGS, false,
radv_device_fault_detection_enabled(device), false);
struct radv_shader_info info = {0};
info.stage = MESA_SHADER_FRAGMENT;

3
src/amd/vulkan/radv_sqtt.c
View file

@ -577,6 +577,7 @@ static bool
radv_sqtt_init_queue_event(struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkCommandPool cmd_pool;
VkResult result;
@ -591,7 +592,7 @@ radv_sqtt_init_queue_event(struct radv_device *device)
device->sqtt_command_pool[0] = vk_command_pool_from_handle(cmd_pool);
if (!(pdev->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
if (!(instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
const VkCommandPoolCreateInfo create_comp_info = {
.sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO,
.queueFamilyIndex = RADV_QUEUE_COMPUTE,

10
src/amd/vulkan/radv_video.c
View file

@ -53,7 +53,9 @@
static bool
radv_enable_tier2(struct radv_physical_device *pdev)
{
if (pdev->info.vcn_ip_version >= VCN_3_0_0 && !(pdev->instance->debug_flags & RADV_DEBUG_VIDEO_ARRAY_PATH))
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (pdev->info.vcn_ip_version >= VCN_3_0_0 && !(instance->debug_flags & RADV_DEBUG_VIDEO_ARRAY_PATH))
return true;
return false;
}
@ -348,11 +350,12 @@ radv_CreateVideoSessionKHR(VkDevice _device, const VkVideoSessionCreateInfoKHR *
{
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_video_session *vid =
vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*vid), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!vid)
return vk_error(pdev->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
memset(vid, 0, sizeof(struct radv_video_session));
@ -416,10 +419,11 @@ radv_CreateVideoSessionParametersKHR(VkDevice _device, const VkVideoSessionParam
RADV_FROM_HANDLE(radv_video_session, vid, pCreateInfo->videoSession);
RADV_FROM_HANDLE(radv_video_session_params, templ, pCreateInfo->videoSessionParametersTemplate);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
struct radv_video_session_params *params =
vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*params), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!params)
return vk_error(pdev->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
VkResult result =
vk_video_session_parameters_init(&device->vk, &params->vk, &vid->vk, templ ? &templ->vk : NULL, pCreateInfo);

18
src/amd/vulkan/radv_wsi.c
View file

@ -36,7 +36,8 @@ static VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
radv_wsi_proc_addr(VkPhysicalDevice physicalDevice, const char *pName)
{
RADV_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
return vk_instance_get_proc_addr_unchecked(&pdev->instance->vk, pName);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
return vk_instance_get_proc_addr_unchecked(&instance->vk, pName);
}
static void
@ -55,11 +56,12 @@ radv_wsi_get_prime_blit_queue(VkDevice _device)
{
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
if (device->private_sdma_queue != VK_NULL_HANDLE)
return vk_queue_to_handle(&device->private_sdma_queue->vk);
if (pdev->info.gfx_level >= GFX9 && !(pdev->instance->debug_flags & RADV_DEBUG_NO_DMA_BLIT)) {
if (pdev->info.gfx_level >= GFX9 && !(instance->debug_flags & RADV_DEBUG_NO_DMA_BLIT)) {
pdev->vk_queue_to_radv[pdev->num_queues++] = RADV_QUEUE_TRANSFER;
const VkDeviceQueueCreateInfo queue_create = {
@ -85,9 +87,11 @@ radv_wsi_get_prime_blit_queue(VkDevice _device)
VkResult
radv_init_wsi(struct radv_physical_device *pdev)
{
VkResult result = wsi_device_init(&pdev->wsi_device, radv_physical_device_to_handle(pdev), radv_wsi_proc_addr,
&pdev->instance->vk.alloc, pdev->master_fd, &pdev->instance->drirc.options,
&(struct wsi_device_options){.sw_device = false});
const struct radv_instance *instance = radv_physical_device_instance(pdev);
VkResult result =
wsi_device_init(&pdev->wsi_device, radv_physical_device_to_handle(pdev), radv_wsi_proc_addr, &instance->vk.alloc,
pdev->master_fd, &instance->drirc.options, &(struct wsi_device_options){.sw_device = false});
if (result != VK_SUCCESS)
return result;
@ -105,6 +109,8 @@ radv_init_wsi(struct radv_physical_device *pdev)
void
radv_finish_wsi(struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
pdev->vk.wsi_device = NULL;
wsi_device_finish(&pdev->wsi_device, &pdev->instance->vk.alloc);
wsi_device_finish(&pdev->wsi_device, &instance->vk.alloc);
}