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radv: add radv_physical_device.h

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28526>
This commit is contained in:
Samuel Pitoiset 2024-04-01 18:37:30 +02:00 • committed by Marge Bot
parent 0fb19b8331
commit 6849305a86
5 changed files with 272 additions and 218 deletions
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1
src/amd/vulkan/meta/radv_meta.h
View file

@ -31,6 +31,7 @@
#include "radv_device_memory.h"
#include "radv_image.h"
#include "radv_image_view.h"
#include "radv_physical_device.h"
#include "radv_private.h"
#include "radv_queue.h"
#include "radv_shader.h"

1
src/amd/vulkan/nir/radv_nir_lower_io.c
View file

@ -27,6 +27,7 @@
#include "nir.h"
#include "nir_builder.h"
#include "radv_nir.h"
#include "radv_physical_device.h"
#include "radv_private.h"
#include "radv_shader.h"

1
src/amd/vulkan/radv_android.c
View file

@ -24,6 +24,7 @@
#include "radv_buffer.h"
#include "radv_device_memory.h"
#include "radv_image.h"
#include "radv_physical_device.h"
#include "radv_private.h"
#if DETECT_OS_ANDROID

268
src/amd/vulkan/radv_physical_device.h Normal file
View file

@ -0,0 +1,268 @@
/*
* Copyright © 2016 Red Hat.
* Copyright © 2016 Bas Nieuwenhuizen
*
* based in part on anv driver which is:
* Copyright © 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef RADV_PHYSICAL_DEVICE_H
#define RADV_PHYSICAL_DEVICE_H
#include "ac_gpu_info.h"
#include "ac_perfcounter.h"
#include "radv_instance.h"
#include "radv_queue.h"
#include "radv_radeon_winsys.h"
#include "wsi_common.h"
#include "nir.h"
#include "vk_physical_device.h"
#ifndef _WIN32
#include <amdgpu.h>
#include <xf86drm.h>
#endif
struct radv_binning_settings {
unsigned context_states_per_bin; /* allowed range: [1, 6] */
unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
};
struct radv_physical_device_cache_key {
enum radeon_family family;
uint32_t ptr_size;
uint32_t conformant_trunc_coord : 1;
uint32_t clear_lds : 1;
uint32_t cs_wave32 : 1;
uint32_t disable_aniso_single_level : 1;
uint32_t disable_shrink_image_store : 1;
uint32_t disable_sinking_load_input_fs : 1;
uint32_t dual_color_blend_by_location : 1;
uint32_t emulate_rt : 1;
uint32_t ge_wave32 : 1;
uint32_t invariant_geom : 1;
uint32_t lower_discard_to_demote : 1;
uint32_t mesh_fast_launch_2 : 1;
uint32_t no_fmask : 1;
uint32_t no_ngg_gs : 1;
uint32_t no_rt : 1;
uint32_t ps_wave32 : 1;
uint32_t rt_wave64 : 1;
uint32_t split_fma : 1;
uint32_t ssbo_non_uniform : 1;
uint32_t tex_non_uniform : 1;
uint32_t use_llvm : 1;
uint32_t use_ngg : 1;
uint32_t use_ngg_culling : 1;
};
struct radv_physical_device {
struct vk_physical_device vk;
struct radeon_winsys *ws;
struct radeon_info info;
char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
char marketing_name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
uint8_t driver_uuid[VK_UUID_SIZE];
uint8_t device_uuid[VK_UUID_SIZE];
uint8_t cache_uuid[VK_UUID_SIZE];
int local_fd;
int master_fd;
struct wsi_device wsi_device;
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
/* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */
bool use_fmask;
/* Whether to enable NGG. */
bool use_ngg;
/* Whether to enable NGG culling. */
bool use_ngg_culling;
/* Whether to enable NGG streamout. */
bool use_ngg_streamout;
/* Whether to emulate the number of primitives generated by GS. */
bool emulate_ngg_gs_query_pipeline_stat;
/* Whether to use GS_FAST_LAUNCH(2) for mesh shaders. */
bool mesh_fast_launch_2;
/* Whether to emulate mesh/task shader queries. */
bool emulate_mesh_shader_queries;
/* Number of threads per wave. */
uint8_t ps_wave_size;
uint8_t cs_wave_size;
uint8_t ge_wave_size;
uint8_t rt_wave_size;
/* Maximum compute shared memory size. */
uint32_t max_shared_size;
/* Whether to use the LLVM compiler backend */
bool use_llvm;
/* Whether to emulate ETC2 image support on HW without support. */
bool emulate_etc2;
/* Whether to emulate ASTC image support on HW without support. */
bool emulate_astc;
VkPhysicalDeviceMemoryProperties memory_properties;
enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
unsigned heaps;
/* Bitmask of memory types that use the 32-bit address space. */
uint32_t memory_types_32bit;
#ifndef _WIN32
int available_nodes;
drmPciBusInfo bus_info;
dev_t primary_devid;
dev_t render_devid;
#endif
nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
enum radv_queue_family vk_queue_to_radv[RADV_MAX_QUEUE_FAMILIES];
uint32_t num_queues;
uint32_t gs_table_depth;
struct ac_hs_info hs;
struct ac_task_info task_info;
struct radv_binning_settings binning_settings;
/* Performance counters. */
struct ac_perfcounters ac_perfcounters;
uint32_t num_perfcounters;
struct radv_perfcounter_desc *perfcounters;
struct {
unsigned data0;
unsigned data1;
unsigned cmd;
unsigned cntl;
} vid_dec_reg;
enum amd_ip_type vid_decode_ip;
uint32_t vid_addr_gfx_mode;
uint32_t stream_handle_base;
uint32_t stream_handle_counter;
uint32_t av1_version;
struct radv_physical_device_cache_key cache_key;
};
VK_DEFINE_HANDLE_CASTS(radv_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
static inline struct radv_instance *
radv_physical_device_instance(const struct radv_physical_device *pdev)
{
return (struct radv_instance *)pdev->vk.instance;
}
static inline bool
radv_sparse_queue_enabled(const struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Dedicated sparse queue requires VK_QUEUE_SUBMIT_MODE_THREADED, which is incompatible with
* VK_DEVICE_TIMELINE_MODE_EMULATED. */
return pdev->info.has_timeline_syncobj && !instance->drirc.legacy_sparse_binding;
}
static inline bool
radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdev, unsigned bitsize)
{
return (pdev->info.gfx_level <= GFX7 && !pdev->use_llvm) || pdev->info.gfx_level == GFX10 ||
pdev->info.gfx_level == GFX10_3 || (pdev->info.gfx_level == GFX11 && bitsize == 32);
}
static inline bool
radv_has_pops(const struct radv_physical_device *pdev)
{
return pdev->info.gfx_level >= GFX9 && !pdev->use_llvm;
}
static inline bool
radv_has_uvd(struct radv_physical_device *phys_dev)
{
enum radeon_family family = phys_dev->info.family;
/* Only support UVD on TONGA+ */
if (family < CHIP_TONGA)
return false;
return phys_dev->info.ip[AMD_IP_UVD].num_queues > 0;
}
static inline enum radv_queue_family
vk_queue_to_radv(const struct radv_physical_device *phys_dev, int queue_family_index)
{
if (queue_family_index == VK_QUEUE_FAMILY_EXTERNAL || queue_family_index == VK_QUEUE_FAMILY_FOREIGN_EXT)
return RADV_QUEUE_FOREIGN;
if (queue_family_index == VK_QUEUE_FAMILY_IGNORED)
return RADV_QUEUE_IGNORED;
assert(queue_family_index < RADV_MAX_QUEUE_FAMILIES);
return phys_dev->vk_queue_to_radv[queue_family_index];
}
/**
* Helper used for debugging compiler issues by enabling/disabling LLVM for a
* specific shader stage (developers only).
*/
static inline bool
radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
{
return pdev->use_llvm;
}
bool radv_enable_rt(const struct radv_physical_device *pdev, bool rt_pipelines);
bool radv_emulate_rt(const struct radv_physical_device *pdev);
bool radv_device_supports_etc(const struct radv_physical_device *pdev);
uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
VkResult create_null_physical_device(struct vk_instance *vk_instance);
VkResult create_drm_physical_device(struct vk_instance *vk_instance, struct _drmDevice *device,
struct vk_physical_device **out);
void radv_physical_device_destroy(struct vk_physical_device *vk_pdev);
#endif /* RADV_PHYSICAL_DEVICE_H */

219
src/amd/vulkan/radv_private.h
View file

@ -80,7 +80,7 @@
#include "ac_vcn.h"
#include "radv_constants.h"
#include "radv_descriptor_set.h"
#include "radv_instance.h"
#include "radv_physical_device.h"
#include "radv_queue.h"
#include "radv_radeon_winsys.h"
#include "radv_shader.h"
@ -209,162 +209,6 @@ struct rvcn_decode_buffer_s;
/* queue types */
struct radv_binning_settings {
unsigned context_states_per_bin; /* allowed range: [1, 6] */
unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
};
struct radv_physical_device_cache_key {
enum radeon_family family;
uint32_t ptr_size;
uint32_t conformant_trunc_coord : 1;
uint32_t clear_lds : 1;
uint32_t cs_wave32 : 1;
uint32_t disable_aniso_single_level : 1;
uint32_t disable_shrink_image_store : 1;
uint32_t disable_sinking_load_input_fs : 1;
uint32_t dual_color_blend_by_location : 1;
uint32_t emulate_rt : 1;
uint32_t ge_wave32 : 1;
uint32_t invariant_geom : 1;
uint32_t lower_discard_to_demote : 1;
uint32_t mesh_fast_launch_2 : 1;
uint32_t no_fmask : 1;
uint32_t no_ngg_gs : 1;
uint32_t no_rt : 1;
uint32_t ps_wave32 : 1;
uint32_t rt_wave64 : 1;
uint32_t split_fma : 1;
uint32_t ssbo_non_uniform : 1;
uint32_t tex_non_uniform : 1;
uint32_t use_llvm : 1;
uint32_t use_ngg : 1;
uint32_t use_ngg_culling : 1;
};
struct radv_physical_device {
struct vk_physical_device vk;
struct radeon_winsys *ws;
struct radeon_info info;
char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
char marketing_name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
uint8_t driver_uuid[VK_UUID_SIZE];
uint8_t device_uuid[VK_UUID_SIZE];
uint8_t cache_uuid[VK_UUID_SIZE];
int local_fd;
int master_fd;
struct wsi_device wsi_device;
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
/* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */
bool use_fmask;
/* Whether to enable NGG. */
bool use_ngg;
/* Whether to enable NGG culling. */
bool use_ngg_culling;
/* Whether to enable NGG streamout. */
bool use_ngg_streamout;
/* Whether to emulate the number of primitives generated by GS. */
bool emulate_ngg_gs_query_pipeline_stat;
/* Whether to use GS_FAST_LAUNCH(2) for mesh shaders. */
bool mesh_fast_launch_2;
/* Whether to emulate mesh/task shader queries. */
bool emulate_mesh_shader_queries;
/* Number of threads per wave. */
uint8_t ps_wave_size;
uint8_t cs_wave_size;
uint8_t ge_wave_size;
uint8_t rt_wave_size;
/* Maximum compute shared memory size. */
uint32_t max_shared_size;
/* Whether to use the LLVM compiler backend */
bool use_llvm;
/* Whether to emulate ETC2 image support on HW without support. */
bool emulate_etc2;
/* Whether to emulate ASTC image support on HW without support. */
bool emulate_astc;
VkPhysicalDeviceMemoryProperties memory_properties;
enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
unsigned heaps;
/* Bitmask of memory types that use the 32-bit address space. */
uint32_t memory_types_32bit;
#ifndef _WIN32
int available_nodes;
drmPciBusInfo bus_info;
dev_t primary_devid;
dev_t render_devid;
#endif
nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
enum radv_queue_family vk_queue_to_radv[RADV_MAX_QUEUE_FAMILIES];
uint32_t num_queues;
uint32_t gs_table_depth;
struct ac_hs_info hs;
struct ac_task_info task_info;
struct radv_binning_settings binning_settings;
/* Performance counters. */
struct ac_perfcounters ac_perfcounters;
uint32_t num_perfcounters;
struct radv_perfcounter_desc *perfcounters;
struct {
unsigned data0;
unsigned data1;
unsigned cmd;
unsigned cntl;
} vid_dec_reg;
enum amd_ip_type vid_decode_ip;
uint32_t vid_addr_gfx_mode;
uint32_t stream_handle_base;
uint32_t stream_handle_counter;
uint32_t av1_version;
struct radv_physical_device_cache_key cache_key;
};
static inline struct radv_instance *
radv_physical_device_instance(const struct radv_physical_device *pdev)
{
return (struct radv_instance *)pdev->vk.instance;
}
uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
VkResult create_null_physical_device(struct vk_instance *vk_instance);
VkResult create_drm_physical_device(struct vk_instance *vk_instance, struct _drmDevice *device,
struct vk_physical_device **out);
void radv_physical_device_destroy(struct vk_physical_device *vk_pdev);
VkResult radv_init_wsi(struct radv_physical_device *pdev);
void radv_finish_wsi(struct radv_physical_device *pdev);
@ -673,40 +517,8 @@ struct radv_meta_state {
#define RADV_NUM_HW_CTX (RADEON_CTX_PRIORITY_REALTIME + 1)
static inline bool
radv_sparse_queue_enabled(const struct radv_physical_device *pdev)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
/* Dedicated sparse queue requires VK_QUEUE_SUBMIT_MODE_THREADED, which is incompatible with
* VK_DEVICE_TIMELINE_MODE_EMULATED. */
return pdev->info.has_timeline_syncobj && !instance->drirc.legacy_sparse_binding;
}
static inline enum radv_queue_family
vk_queue_to_radv(const struct radv_physical_device *phys_dev, int queue_family_index)
{
if (queue_family_index == VK_QUEUE_FAMILY_EXTERNAL || queue_family_index == VK_QUEUE_FAMILY_FOREIGN_EXT)
return RADV_QUEUE_FOREIGN;
if (queue_family_index == VK_QUEUE_FAMILY_IGNORED)
return RADV_QUEUE_IGNORED;
assert(queue_family_index < RADV_MAX_QUEUE_FAMILIES);
return phys_dev->vk_queue_to_radv[queue_family_index];
}
enum amd_ip_type radv_queue_family_to_ring(const struct radv_physical_device *dev, enum radv_queue_family f);
static inline bool
radv_has_uvd(struct radv_physical_device *phys_dev)
{
enum radeon_family family = phys_dev->info.family;
/* Only support UVD on TONGA+ */
if (family < CHIP_TONGA)
return false;
return phys_dev->info.ip[AMD_IP_UVD].num_queues > 0;
}
#define RADV_BORDER_COLOR_COUNT 4096
#define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
@ -2023,10 +1835,6 @@ void radv_hash_rt_shaders(const struct radv_device *device, unsigned char *hash,
const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
const struct radv_ray_tracing_group *groups);
bool radv_enable_rt(const struct radv_physical_device *pdev, bool rt_pipelines);
bool radv_emulate_rt(const struct radv_physical_device *pdev);
enum radv_pipeline_type {
RADV_PIPELINE_GRAPHICS,
RADV_PIPELINE_GRAPHICS_LIB,
@ -2376,7 +2184,6 @@ void radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pip
const VkAllocationCallbacks *allocator);
struct vk_format_description;
bool radv_device_supports_etc(const struct radv_physical_device *pdev);
unsigned radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const struct radv_image *image);
@ -2945,29 +2752,6 @@ radv_queue_ring(const struct radv_queue *queue)
return radv_queue_family_to_ring(pdev, queue->state.qf);
}
/**
* Helper used for debugging compiler issues by enabling/disabling LLVM for a
* specific shader stage (developers only).
*/
static inline bool
radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
{
return pdev->use_llvm;
}
static inline bool
radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdev, unsigned bitsize)
{
return (pdev->info.gfx_level <= GFX7 && !pdev->use_llvm) || pdev->info.gfx_level == GFX10 ||
pdev->info.gfx_level == GFX10_3 || (pdev->info.gfx_level == GFX11 && bitsize == 32);
}
static inline bool
radv_has_pops(const struct radv_physical_device *pdev)
{
return pdev->info.gfx_level >= GFX9 && !pdev->use_llvm;
}
unsigned radv_compact_spi_shader_col_format(const struct radv_shader *ps, uint32_t spi_shader_col_format);
/* radv_spm.c */
@ -3031,7 +2815,6 @@ void radv_get_compute_pipeline_metadata(const struct radv_device *device, const
VK_DEFINE_HANDLE_CASTS(radv_cmd_buffer, vk.base, VkCommandBuffer, VK_OBJECT_TYPE_COMMAND_BUFFER)
VK_DEFINE_HANDLE_CASTS(radv_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
VK_DEFINE_HANDLE_CASTS(radv_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_object, base, VkShaderEXT, VK_OBJECT_TYPE_SHADER_EXT);