sed -i "s/nir_src_parent_instr/nir_src_use_instr/" `find ./ -type f`
sed -i "s/nir_src_parent_if/nir_src_use_if/" `find ./ -type f`
sed -i "s/nir_src_set_parent/nir_src_set_use/" `find ./ -type f`
There are two kinds of "parent" in relation to a src/def:
- the instruction where the def or src's def is defined
- the instruction which the src is a part of and where the def is used
Clarify that the parent here is where the src's def is used, not where
it's defined.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41344>
This contains more tests for the SMEM PRT workaround that we implemented
on RADV. VKCTS already has some coverage but it doesn't hurt to have
more.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41356>
CtsDeqpTestCases was originally added to run WSI tests on Android.
This is now covered by the command-line dEQP executable, which produces
comparable results and is much, much faster thanks to multithreading via
deqp-runner.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
We can now run dEQP-VK.wsi.android.* and more EGL tests with ANGLE in the
deqp-runner suite.
The regular VKCTS test set had to be reduced to fit within the time
limit.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
We can now run dEQP-VK.wsi.android.* and more EGL tests with ANGLE in the
deqp-runner suite.
The regular VKCTS test set had to be reduced to fit within the time
limit.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
We can now run dEQP-VK.wsi.android.* and more EGL tests with ANGLE in the
deqp-runner suite.
This shows a Lavapipe bug.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
This is implement with a headless WSI fallback using AImageReader, which
allows running EGL and Vulkan WSI tests from the command-line executable
(DEQP_ANDROID_EXE) on Android.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
- gralloc0: fix the FRONT_RENDERING_BIT private query in minigbm
- Fixes enabling VK_KHR_shared_presentable_image
- Update Mesa to latest main, 117f3cb1fc ("gfxstream: allow
VK_KHR_maintenance extensions")
- Fixes a Turnip crash before the driver is replaced in the CI pipeline
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
The combined $ADB wait-for-device root command can be flaky with
Cuttlefish, sometimes failing with:
"adb: unable to connect for root: closed"
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41314>
On LINEAR_PE GPUs, shared linear resources are render-compatible so
no render shadow exists - the PE renders directly into the shared
buffer. Rather than adding a dedicated flush-time blit to swap R/B
(which would introduce bandwidth that doesn't exist today), use the
frag_rb_swap shader key to swap channels at render time.
In etna_draw_vbo, detect LINEAR_PE + shared + linear + RB_SWAP format
and set the per-RT frag_rb_swap bits. Track shared_native_order so
etna_flush_resource can skip the dedicated blit when the shader
already produced correct byte order.
Fixes: a5766e75e48 ("etnaviv: Use BGRA-internal texture format with BLT/RS R/B swizzle")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40029>
Add a per-RT bitmask to the shader key that triggers R/B channel
swapping in the fragment shader output. Handles scalar through vec4
outputs by widening to vec4 first, then swapping channels 0 and 2
with adjusted writemask.
Preparation for LINEAR_PE GPUs where shared linear resources have no
render shadow, so the shader must produce correct byte order directly.
No functional change - nothing sets frag_rb_swap yet.
Fixes: a5766e75e48 ("etnaviv: Use BGRA-internal texture format with BLT/RS R/B swizzle")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40029>
The previous patches statically remapped the texture format at sampler
view creation time (A8R8G8B8 -> A8B8G8R8) for shared resources with
RB_SWAP formats. This is correct when the shared buffer holds
externally-produced RGBA data (import) or after flush_resource has done
the R<->B swap.
However, if the PE renders directly to a shared buffer (LINEAR_PE, no
render shadow), the data becomes BGRA. The static A8B8G8R8 format then
reads BGRA as RGBA - R and B are swapped.
Fix this by tracking whether the shared buffer holds native (RGBA) or
PE-internal (BGRA) byte order via a new shared_native_order flag, and
selecting the texture format dynamically at emit time.
The flag is set to true on import and export (data is native byte order
at that point), cleared when the PE renders directly to a shared buffer
without a render shadow, and set back to true after flush_resource
performs the R<->B swap.
Both the state-based and descriptor-based texture paths pre-compute the
native format variant at sampler view creation time, avoiding any
per-frame overhead beyond a single branch in the emit path.
Fixes: a5766e75e48 ("etnaviv: Use BGRA-internal texture format with BLT/RS R/B swizzle")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40029>
The PE renders RB_SWAP formats (e.g. R8G8B8A8_UNORM) using the A8R8G8B8
hardware format, which stores data in BGRA byte order internally. For
shared/dmabuf resources, external consumers expect the byte order
mandated by the DRM FourCC.
Hook into flush_resource to apply an R<->B swap during the existing
shadow-to-base copy, using the BLT dest swizzle or RS SWAP_RB.
Fixes: a5766e75e48 ("etnaviv: Use BGRA-internal texture format with BLT/RS R/B swizzle")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40029>
The rb-swap rework (commit a5766e75e48) uses A8R8G8B8 as the texture
format for RB_SWAP pipe formats and performs R<->B conversion during
transfer blits. This breaks dmabuf import/export: external producers
write RGBA bytes, but A8R8G8B8 interprets them as BGRA; transfer blits
incorrectly swap R<->B on data already in the correct byte order.
For shared/imported resources, bypass the optimization: use the native
texture format (A8B8G8R8) so the sampler reads RGBA bytes correctly in
both the descriptor and state-based texture paths, skip the R<->B
swizzle in BLT and RS transfer blits since shared resources already
store data in standard byte order, and re-enable the texture shadow
shortcut for shared RB_SWAP resources since the BLT swap is no longer
applied.
Internal-only resources continue using the BGRA-internal optimization
unchanged.
Fixes: a5766e75e48 ("etnaviv: Use BGRA-internal texture format with BLT/RS R/B swizzle")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40029>
This platform just needs a bit more care around vertex buffer state
emission.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
Some kernel will be to large and potentially change too often to
really have a consistent count.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
Up to now all push descriptor accesses where going through the binding
table. That's not going to be the case anymore with descriptor buffers
device bindable shaders. Those will do A64 messages to read the
descriptor buffer (for example when build a bounded 64bit address for
storage buffers, or 64bit image format atomic emulation, etc...)
We need to have the offset relative to the push descriptor heap
(internal_state_heap in this case).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
When we don't know what shader is executed. We'll still have the bind
map from the indirect execution set.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
We consider them like bindless stages (no binding table) as much as
possible.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
We'll want to access those on the device, so having them without any
host related things is nice.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
It'll be useful for DGC preprocessing where we need to extract some
state programming from the command buffer, yet pointer programming is
not required to be flushed.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
Several things were wrong :
- incorrect offset in the FS push constant data
- incorrect encoding of the 32bit values with 2 fields (remap table offset & provoking vertex)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
The QPU prefetches the next instruction during shader execution.
If the shader assembly size perfectly aligns with a page boundary,
the prefetching mechanism reads past the compiled boundary,
leading to an MMU error.
This commit insert an explicit NOP instruction at the end of the shader
and increases the qpu_inst_count by one when the instruction count
exactly hits a page boundary. This ensures we don't fall off the end
of the last executable instruction page and into invalid memory.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40983>
