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radv,ac: make rembrandt and vangogh cache compatible
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41340>
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parent
ec59b59b97
commit
6e06012825
10 changed files with 32 additions and 11 deletions
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@ -1558,6 +1558,9 @@ RADV driver environment variables
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Enable tracking of VA ranges for radv_build_is_valid_va.
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``vm``
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add a gap between all VA allocations to check for page faults
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``nocachecompat``
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disable changes to code generation which increases shader cache compatiblity
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between devices
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.. envvar:: RADV_QUEUE_DISABLE
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@ -234,7 +234,8 @@ static bool handle_env_var_force_family(struct radeon_info *info)
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}
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void
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ac_fill_compiler_info(struct radeon_info *info, const struct drm_amdgpu_info_device *device_info)
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ac_fill_compiler_info(struct radeon_info *info, const struct drm_amdgpu_info_device *device_info,
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bool compat_mode)
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{
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/* We use ac_compiler_info for shader cache keys, so make sure there is no padding. */
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STATIC_ASSERT(sizeof(enum amd_gfx_level) == 4);
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@ -420,6 +421,11 @@ ac_fill_compiler_info(struct radeon_info *info, const struct drm_amdgpu_info_dev
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* Only GFX9 works as expected.
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*/
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out->has_smem_with_null_prt_bug = info->gfx_level <= GFX12 && info->gfx_level != GFX9;
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if (compat_mode && info->family == CHIP_REMBRANDT) {
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out->has_ngg_passthru_no_msg = false;
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out->has_vrs_frag_pos_z_bug = true;
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}
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}
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void
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@ -1390,7 +1396,7 @@ void ac_fill_tess_info(struct radeon_info *info)
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enum ac_query_gpu_info_result
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ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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bool require_pci_bus_info)
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bool require_pci_bus_info, bool compiler_compat_mode)
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{
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struct amdgpu_gpu_info amdinfo;
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struct drm_amdgpu_info_device device_info = {0};
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@ -1563,7 +1569,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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ac_fill_tess_info(info);
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ac_fill_compiler_info(info, &device_info);
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ac_fill_compiler_info(info, &device_info, compiler_compat_mode);
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/* BIG_PAGE is supported since gfx10.3 and requires VRAM. VRAM is only guaranteed
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* with AMDGPU_GEM_CREATE_DISCARDABLE.
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@ -490,9 +490,18 @@ enum ac_query_gpu_info_result {
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AC_QUERY_GPU_INFO_UNIMPLEMENTED_HW,
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};
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/* If compiler_compat_mode is true, then ac_compiler_info must be identical between:
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* - CHIP_VANGOGH and CHIP_REMBRANDT
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* - CHIP_NAVI33, CHIP_PHOENIX and CHIP_PHOENIX2
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* This is done by disabling features and enabling workarounds.
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*
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* conformant_trunc_coord is an exception, and might differ.
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*/
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enum ac_query_gpu_info_result ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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bool require_pci_bus_info);
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void ac_fill_compiler_info(struct radeon_info *info, const struct drm_amdgpu_info_device *device_info);
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bool require_pci_bus_info,
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bool compiler_compat_mode);
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void ac_fill_compiler_info(struct radeon_info *info,
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const struct drm_amdgpu_info_device *device_info, bool compat_mode);
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void ac_fill_tiling_info(struct radeon_info *info, const struct amdgpu_gpu_info *amdinfo);
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void ac_fill_memory_info(struct radeon_info *info, const struct drm_amdgpu_info_device *device_info,
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const struct drm_amdgpu_memory_info *meminfo);
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@ -94,7 +94,7 @@ static void get_radeon_info(struct radeon_info *info, const struct ac_surface_fa
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ac_fill_feature_info(info, &dev->dev);
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ac_fill_bug_info(info);
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ac_fill_tess_info(info);
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ac_fill_compiler_info(info, &dev->dev);
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ac_fill_compiler_info(info, &dev->dev, false);
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switch(info->gfx_level) {
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case GFX9:
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@ -97,7 +97,7 @@ create_program(enum amd_gfx_level gfx_level, Stage stage, unsigned wave_size,
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program.reset(new Program);
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rad_info.gfx_level = gfx_level;
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rad_info.family = family;
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ac_fill_compiler_info(&rad_info, NULL);
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ac_fill_compiler_info(&rad_info, NULL, false);
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struct aco_compiler_options options = {
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.compiler_info = &rad_info.compiler_info,
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.family = family,
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@ -174,7 +174,7 @@ setup_nir_cs(enum amd_gfx_level gfx_level, mesa_shader_stage stage, enum radeon_
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memset(&rad_info, 0, sizeof(rad_info));
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rad_info.gfx_level = gfx_level;
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rad_info.family = family;
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ac_fill_compiler_info(&rad_info, NULL);
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ac_fill_compiler_info(&rad_info, NULL, false);
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memset(&nir_options, 0, sizeof(nir_options));
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ac_nir_set_options(&rad_info.compiler_info, false, &nir_options);
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@ -15,6 +15,7 @@
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enum {
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RADV_DEBUG_NO_FAST_CLEARS = 1ull << 0,
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RADV_DEBUG_NO_DCC = 1ull << 1,
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RADV_DEBUG_NO_CACHE_COMPAT = 1ull << 2,
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RADV_DEBUG_NO_CACHE = 1ull << 3,
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RADV_DEBUG_DUMP_SHADER_STATS = 1ull << 4,
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RADV_DEBUG_NO_HIZ = 1ull << 5,
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@ -30,6 +30,7 @@ static const struct debug_control radv_debug_options[] = {
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{"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
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{"nodcc", RADV_DEBUG_NO_DCC},
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{"shaders", RADV_DEBUG_DUMP_SHADERS},
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{"nocachecompat", RADV_DEBUG_NO_CACHE_COMPAT},
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{"nocache", RADV_DEBUG_NO_CACHE},
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{"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
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{"nohiz", RADV_DEBUG_NO_HIZ},
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@ -299,7 +299,8 @@ radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags,
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ws->info.drm_minor = drm_minor;
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ws->info.is_virtio = is_virtio;
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enum ac_query_gpu_info_result info_result = ac_query_gpu_info(fd, ws->dev, &ws->info, true);
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enum ac_query_gpu_info_result info_result =
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ac_query_gpu_info(fd, ws->dev, &ws->info, true, !(debug_flags & RADV_DEBUG_NO_CACHE_COMPAT));
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if (info_result != AC_QUERY_GPU_INFO_SUCCESS) {
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result = info_result == AC_QUERY_GPU_INFO_FAIL ? VK_ERROR_INITIALIZATION_FAILED : VK_ERROR_INCOMPATIBLE_DRIVER;
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goto winsys_fail;
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@ -44,7 +44,7 @@ static bool do_winsys_init(struct amdgpu_winsys *aws,
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const struct pipe_screen_config *config,
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int fd)
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{
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if (ac_query_gpu_info(fd, aws->dev, &aws->info, false) != AC_QUERY_GPU_INFO_SUCCESS) {
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if (ac_query_gpu_info(fd, aws->dev, &aws->info, false, false) != AC_QUERY_GPU_INFO_SUCCESS) {
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mesa_loge("amdgpu: ac_query_gpu_info failed.\n");
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goto fail;
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}
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@ -641,7 +641,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
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ws->info.tcp_cache_size = 16 * 1024;
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#ifdef HAVE_GALLIUM_RADEONSI
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ac_fill_compiler_info(&ws->info, NULL);
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ac_fill_compiler_info(&ws->info, NULL, false);
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#endif
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for (unsigned se = 0; se < ws->info.max_se; se++) {
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