mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 02:48:06 +02:00
anv: add indirect command layout support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>
This commit is contained in:
Lionel Landwerlin
Marge Bot
parent
68885511d2
commit
fb26ed6bf7
4 changed files with 847 additions and 0 deletions
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@ -40,6 +40,69 @@ genX_xml_h = custom_target(
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genX_bits_included_symbols = [
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# instructions
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'COMPUTE_WALKER',
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'GPGPU_WALKER',
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'MEDIA_CURBE_LOAD',
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'MEDIA_INTERFACE_DESCRIPTOR_LOAD',
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'MEDIA_STATE_FLUSH',
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'MEDIA_VFE_STATE',
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'MI_ARB_CHECK',
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'3DMESH_3D',
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'3DPRIMITIVE',
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'3DPRIMITIVE_EXTENDED',
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'3DSTATE_CLEAR_PARAMS',
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'3DSTATE_CLIP',
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'3DSTATE_CLIP_MESH',
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'3DSTATE_CONSTANT_ALL',
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'3DSTATE_CONSTANT_VS',
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'3DSTATE_DS',
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'3DSTATE_GS',
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'3DSTATE_HS',
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'3DSTATE_INDEX_BUFFER',
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'3DSTATE_MESH_CONTROL',
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'3DSTATE_MESH_DISTRIB',
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'3DSTATE_MESH_SHADER',
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'3DSTATE_MESH_SHADER_DATA',
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'3DSTATE_PRIMITIVE_REPLICATION',
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'3DSTATE_PS',
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'3DSTATE_PS_BLEND',
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'3DSTATE_PS_EXTRA',
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'3DSTATE_PUSH_CONSTANT_ALLOC_VS',
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'3DSTATE_RASTER',
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'3DSTATE_SBE',
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'3DSTATE_SBE_MESH',
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'3DSTATE_SBE_SWIZ',
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'3DSTATE_SF',
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'3DSTATE_STREAMOUT',
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'3DSTATE_TASK_CONTROL',
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'3DSTATE_TASK_REDISTRIB',
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'3DSTATE_TASK_SHADER',
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'3DSTATE_TASK_SHADER_DATA',
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'3DSTATE_TE',
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'3DSTATE_URB_ALLOC_MESH',
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'3DSTATE_URB_ALLOC_TASK',
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'3DSTATE_URB_ALLOC_VS',
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'3DSTATE_URB_VS',
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'3DSTATE_VF_INSTANCING',
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'3DSTATE_VF_SGVS',
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'3DSTATE_VF_SGVS_2',
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'3DSTATE_VF_TOPOLOGY',
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'3DSTATE_VFG',
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'3DSTATE_WM',
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'3DSTATE_VS',
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'PIPE_CONTROL',
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'RESOURCE_BARRIER',
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# instruction fields
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'3DSTATE_CPSIZE_CONTROL_BUFFER::Surface Base Address',
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'3DSTATE_CPSIZE_CONTROL_BUFFER::Surface Pitch',
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'3DSTATE_DEPTH_BUFFER::Surface Base Address',
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'3DSTATE_DEPTH_BUFFER::Surface Pitch',
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'3DSTATE_HIER_DEPTH_BUFFER::Surface Base Address',
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'3DSTATE_HIER_DEPTH_BUFFER::Surface Pitch',
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'3DSTATE_STENCIL_BUFFER::Surface Base Address',
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'3DSTATE_STENCIL_BUFFER::Surface Pitch',
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'3DSTATE_SO_BUFFER::Surface Base Address',
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'3DSTATE_SO_BUFFER::Stream Offset',
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'MI_BATCH_BUFFER_START::Batch Buffer Start Address',
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'MI_REPORT_PERF_COUNT::Memory Address',
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'MI_STORE_DATA_IMM::Address',
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@ -61,6 +124,7 @@ genX_bits_included_symbols = [
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'COMPUTE_WALKER::body',
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'EXECUTE_INDIRECT_DISPATCH::body',
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# structures
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'3DSTATE_CONSTANT_ALL_DATA',
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'RENDER_SURFACE_STATE::Surface Base Address',
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'RENDER_SURFACE_STATE::Surface Pitch',
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'RENDER_SURFACE_STATE::Surface QPitch',
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@ -81,6 +145,7 @@ genX_bits_included_symbols = [
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'CLEAR_COLOR',
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'VERTEX_BUFFER_STATE::Buffer Starting Address',
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'CPS_STATE',
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'INTERFACE_DESCRIPTOR_DATA',
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'RT_DISPATCH_GLOBALS::Hit Group Table',
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'RT_DISPATCH_GLOBALS::Miss Group Table',
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'RT_DISPATCH_GLOBALS::Callable Group Table',
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@ -91,6 +156,7 @@ genX_bits_included_symbols = [
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'RT_DISPATCH_GLOBALS::Launch Height',
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'RT_DISPATCH_GLOBALS::Launch Depth',
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'SAMPLER_STATE',
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'VERTEX_ELEMENT_STATE',
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]
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genX_bits_h = custom_target(
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707
src/intel/vulkan/anv_dgc_layout.c
Normal file
707
src/intel/vulkan/anv_dgc_layout.c
Normal file
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@ -0,0 +1,707 @@
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/*
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* Copyright 2024 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "genxml/genX_bits.h"
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#include "shaders/libintel_shaders.h"
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#include "anv_private.h"
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/* The DGC preprocess command buffer layout is separated in 4 parts:
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*
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* +--------+----------+--------+------+
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* | prolog | commands | epilog | data |
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* +--------+----------+--------+------+
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*
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* The prolog consist of a few commands to deal with the command buffer
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* prefetch and editing some the return address in the epilog part.
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*
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* The commands is where the generated commands are located.
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*
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* The epilog is where the jump back to the calling command buffer happens.
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*
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* Data is where things like INTERFACE_DESCRIPTOR_DATA is located (on pre
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* Gfx12.5) and the push constant data used by the commands.
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*/
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static uint32_t
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draw_cmd_size(const struct intel_device_info *devinfo,
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const struct vk_indirect_command_layout *vk_layout)
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{
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return 4 *
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((vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) ?
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_3DMESH_3D_length(devinfo) :
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devinfo->ver >= 11 ? _3DPRIMITIVE_EXTENDED_length(devinfo) :
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_3DPRIMITIVE_length(devinfo));
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}
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static void
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layout_add_command(struct anv_indirect_command_layout *layout, uint32_t size,
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const char *name)
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{
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layout->cmd_size = align(layout->cmd_size, 4);
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layout->cmd_size += size;
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layout->items[layout->n_items++] = (struct anv_indirect_command_layout_item) {
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.name = name,
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.size = size,
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};
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}
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static void
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layout_add_data(struct anv_indirect_command_layout *layout,
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uint32_t size, uint32_t alignment,
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uint16_t *out_data_offset)
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{
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layout->data_size = align(layout->data_size, alignment);
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if (out_data_offset)
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*out_data_offset = layout->data_size;
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layout->data_size += size;
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}
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static void
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push_layout_add_range(struct anv_dgc_push_layout *pc_layout,
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const struct vk_indirect_command_push_constant_layout *vk_pc_layout)
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{
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pc_layout->entries[pc_layout->num_entries++] = (struct anv_dgc_push_entry) {
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.seq_offset = vk_pc_layout->src_offset_B,
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.push_offset = vk_pc_layout->dst_offset_B,
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.size = vk_pc_layout->size_B,
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};
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}
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static uint32_t
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push_constant_command_size(const struct intel_device_info *devinfo,
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mesa_shader_stage stage,
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uint32_t n_slots)
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{
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uint32_t dwords = 0;
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switch (stage) {
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_TESS_EVAL:
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case MESA_SHADER_GEOMETRY:
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case MESA_SHADER_FRAGMENT:
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if (devinfo->ver >= 12) {
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dwords += (_3DSTATE_CONSTANT_ALL_length(devinfo) +
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n_slots * _3DSTATE_CONSTANT_ALL_DATA_length(devinfo));
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} else {
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dwords += _3DSTATE_CONSTANT_VS_length(devinfo);
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}
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break;
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case MESA_SHADER_MESH:
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dwords += _3DSTATE_MESH_SHADER_DATA_length(devinfo);
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break;
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case MESA_SHADER_TASK:
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dwords += _3DSTATE_TASK_SHADER_DATA_length(devinfo);
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break;
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default:
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UNREACHABLE("Invalid stage");
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}
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return 4 * dwords;
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}
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VkResult anv_CreateIndirectCommandsLayoutEXT(
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VkDevice _device,
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const VkIndirectCommandsLayoutCreateInfoEXT* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkIndirectCommandsLayoutEXT* pIndirectCommandsLayout)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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const struct intel_device_info *devinfo = device->info;
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struct anv_indirect_command_layout *layout_obj;
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layout_obj = vk_indirect_command_layout_create(
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&device->vk, pCreateInfo, pAllocator,
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sizeof(struct anv_indirect_command_layout));
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if (!layout_obj)
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return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
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struct vk_indirect_command_layout *vk_layout = &layout_obj->vk;
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const bool is_gfx =
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(vk_layout->dgc_info &
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(BITFIELD_BIT(MESA_VK_DGC_DRAW) |
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BITFIELD_BIT(MESA_VK_DGC_DRAW_INDEXED) |
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BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH))) != 0;
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struct anv_dgc_gfx_layout *gfx_layout = &layout_obj->gfx_layout;
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struct anv_dgc_cs_layout *cs_layout = &layout_obj->cs_layout;
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struct anv_dgc_push_layout *pc_layout =
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is_gfx ? &gfx_layout->push_constants : &cs_layout->push_constants;
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/* Some checks that the OpenCL code stays in sync. */
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STATIC_ASSERT(ANV_DGC_RT_GLOBAL_DISPATCH_SIZE == BRW_RT_PUSH_CONST_OFFSET);
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/* Keep this in sync with generate_commands.cl:write_prolog_epilog() */
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layout_obj->cmd_prolog_size = 4 *
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(MI_STORE_DATA_IMM_length(devinfo) + 1 +
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MI_BATCH_BUFFER_START_length(devinfo) +
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(devinfo->ver >= 12 ? MI_ARB_CHECK_length(devinfo) : 0));
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layout_obj->cmd_epilog_size = 4 * MI_BATCH_BUFFER_START_length(devinfo);
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/* On <= Gfx12.0 the gl_NumWorkGroups is located in the push constants so
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* we need push constant data per sequence.
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*/
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const bool has_per_sequence_constants = true;
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if (has_per_sequence_constants) {
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/* RT & compute need a combined push constants and also Mesh. */
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uint32_t pc_size = sizeof(struct anv_push_constants);
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/* Prior to Gfx12.5+, there is no HW mechanism in the HW thread
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* generation to provide a workgroup local id. The way the workgroup
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* local id is provided is through a per-thread push constant mechanism
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* that read a per thread 32B (one GRF) piece of data in which the
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* driver writes the thread id.
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*
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* The maximum workgroup size is 1024. With a worse case dispatch size
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* of SIMD8, that means at max 128 HW threads, each needing a 32B for
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* its subgroup_id value within the workgroup. 32B * 128 = 4096B.
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*/
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if (devinfo->verx10 < 125 &&
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(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DISPATCH)))
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pc_size += 4096;
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/* RT_DISPATCH_GLOBALS is located just before the push constant data. */
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_RT))
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pc_size += ANV_DGC_RT_GLOBAL_DISPATCH_SIZE;
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layout_add_data(layout_obj, pc_size, ANV_UBO_ALIGNMENT,
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&pc_layout->data_offset);
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for (uint32_t i = 0; i < vk_layout->n_pc_layouts; i++) {
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const struct vk_indirect_command_push_constant_layout *vk_pc_layout =
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&vk_layout->pc_layouts[i];
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push_layout_add_range(pc_layout, vk_pc_layout);
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}
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_SI)) {
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pc_layout->seq_id_active = true;
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pc_layout->seq_id_offset = vk_layout->si_layout.dst_offset_B;
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}
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pc_layout->mocs =
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isl_mocs(&device->isl_dev, ISL_SURF_USAGE_CONSTANT_BUFFER_BIT, false);
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}
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/* Graphics */
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if (vk_layout->dgc_info & (BITFIELD_BIT(MESA_VK_DGC_DRAW) |
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BITFIELD_BIT(MESA_VK_DGC_DRAW_INDEXED) |
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BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH))) {
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layout_obj->bind_point = VK_PIPELINE_BIND_POINT_GRAPHICS;
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/* 3DSTATE_INDEX_BUFFER */
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IB)) {
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layout_add_command(layout_obj,
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_3DSTATE_INDEX_BUFFER_length(devinfo) * 4,
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"index");
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}
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/* 3DSTATE_VERTEX_BUFFERS */
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_VB)) {
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layout_add_command(layout_obj,
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(1 /* TODO: _3DSTATE_VERTEX_BUFFERS_length(devinfo) */ +
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util_bitcount(vk_layout->vertex_bindings) *
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VERTEX_BUFFER_STATE_length(devinfo)) * 4,
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"vertex");
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}
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if ((vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) == 0) {
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if (intel_needs_workaround(device->info, 16011107343))
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layout_add_command(layout_obj, _3DSTATE_HS_length(devinfo) * 4, "hs");
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if (intel_needs_workaround(device->info, 22018402687))
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layout_add_command(layout_obj, _3DSTATE_DS_length(devinfo) * 4, "ds");
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}
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const VkShaderStageFlags draw_stages =
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(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) ?
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(VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT |
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VK_SHADER_STAGE_FRAGMENT_BIT) :
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(VK_SHADER_STAGE_VERTEX_BIT |
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VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT |
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VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT |
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VK_SHADER_STAGE_GEOMETRY_BIT |
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VK_SHADER_STAGE_FRAGMENT_BIT);
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const bool need_push_constants =
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(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IES)) != 0 ||
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(vk_layout->dgc_info & (BITFIELD_BIT(MESA_VK_DGC_PC) |
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BITFIELD_BIT(MESA_VK_DGC_SI))) != 0;
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/* 3DSTATE_CONSTANT_* */
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if (need_push_constants) {
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uint32_t cmd_size = 0;
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anv_foreach_vk_stage(vk_stage, draw_stages) {
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cmd_size += push_constant_command_size(
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devinfo, vk_to_mesa_shader_stage(vk_stage), 4);
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}
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layout_add_command(layout_obj, cmd_size, "push-constants");
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}
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/* 3DPRIMITIVE / 3DMESH_3D */
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layout_add_command(layout_obj, draw_cmd_size(devinfo, vk_layout), "draw");
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gfx_layout->draw.seq_offset = vk_layout->draw_src_offset_B;
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}
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/* Compute */
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DISPATCH)) {
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layout_obj->bind_point = VK_PIPELINE_BIND_POINT_COMPUTE;
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IES)) {
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cs_layout->indirect_set.active = true;
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cs_layout->indirect_set.seq_offset = vk_layout->ies_src_offset_B;
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}
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cs_layout->dispatch.seq_offset = vk_layout->dispatch_src_offset_B;
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if (devinfo->verx10 >= 125) {
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/* On Gfx12.5+ everything is in a single instruction */
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uint32_t cmd_size = COMPUTE_WALKER_length(devinfo) * 4;
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layout_add_command(layout_obj, cmd_size, "compute-walker");
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} else {
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/* Prior generations */
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uint32_t cmd_size = 4 * (MEDIA_CURBE_LOAD_length(devinfo) +
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GPGPU_WALKER_length(devinfo) +
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MEDIA_STATE_FLUSH_length(devinfo));
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IES)) {
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cmd_size += 4 * (MEDIA_VFE_STATE_length(devinfo) +
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MEDIA_INTERFACE_DESCRIPTOR_LOAD_length(devinfo));
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layout_add_data(layout_obj,
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4 * INTERFACE_DESCRIPTOR_DATA_length(devinfo), 64,
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&cs_layout->indirect_set.data_offset);
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}
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layout_add_command(layout_obj, cmd_size,
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"media-curbe,gpgpu-walker,media-state");
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}
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}
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/* Ray-tracing */
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if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_RT)) {
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layout_obj->bind_point = VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR;
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uint32_t cmd_size = COMPUTE_WALKER_length(devinfo) * 4;
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layout_add_command(layout_obj, cmd_size, "compute-walker");
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cs_layout->dispatch.seq_offset = vk_layout->dispatch_src_offset_B;
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}
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|
||||
layout_obj->data_prolog_size = align(layout_obj->data_prolog_size, 64);
|
||||
layout_obj->data_size = align(layout_obj->data_size, ANV_UBO_ALIGNMENT);
|
||||
|
||||
layout_obj->emits_push_constants =
|
||||
(vk_layout->dgc_info & (BITFIELD_BIT(MESA_VK_DGC_PC) |
|
||||
BITFIELD_BIT(MESA_VK_DGC_SI))) ||
|
||||
((vk_layout->dgc_info & (BITFIELD_BIT(MESA_VK_DGC_DRAW) |
|
||||
BITFIELD_BIT(MESA_VK_DGC_DRAW_INDEXED) |
|
||||
BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH))) &&
|
||||
(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IES)));
|
||||
|
||||
*pIndirectCommandsLayout = anv_indirect_command_layout_to_handle(layout_obj);
|
||||
|
||||
return VK_SUCCESS;
|
||||
}
|
||||
|
||||
void
|
||||
anv_DestroyIndirectCommandsLayoutEXT(
|
||||
VkDevice _device,
|
||||
VkIndirectCommandsLayoutEXT indirectCommandsLayout,
|
||||
const VkAllocationCallbacks* pAllocator)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_device, device, _device);
|
||||
ANV_FROM_HANDLE(anv_indirect_command_layout, layout, indirectCommandsLayout);
|
||||
|
||||
if (!layout)
|
||||
return;
|
||||
|
||||
vk_indirect_command_layout_destroy(&device->vk, pAllocator, &layout->vk);
|
||||
}
|
||||
|
||||
void anv_GetGeneratedCommandsMemoryRequirementsEXT(
|
||||
VkDevice _device,
|
||||
const VkGeneratedCommandsMemoryRequirementsInfoEXT* pInfo,
|
||||
VkMemoryRequirements2* pMemoryRequirements)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_device, device, _device);
|
||||
ANV_FROM_HANDLE(anv_indirect_command_layout, layout_obj,
|
||||
pInfo->indirectCommandsLayout);
|
||||
const struct intel_device_info *devinfo = device->info;
|
||||
|
||||
pMemoryRequirements->memoryRequirements.alignment = 64;
|
||||
pMemoryRequirements->memoryRequirements.size =
|
||||
align(layout_obj->cmd_prolog_size + layout_obj->cmd_epilog_size +
|
||||
pInfo->maxSequenceCount * layout_obj->cmd_size, 64) +
|
||||
align(pInfo->maxSequenceCount * layout_obj->data_size, 64) +
|
||||
align(layout_obj->data_prolog_size, 64);
|
||||
pMemoryRequirements->memoryRequirements.memoryTypeBits =
|
||||
devinfo->verx10 <= 120 ?
|
||||
device->physical->memory.dynamic_visible_mem_types :
|
||||
device->physical->memory.default_buffer_mem_types;
|
||||
|
||||
if (!device->physical->has_scratch_page) {
|
||||
pMemoryRequirements->memoryRequirements.size +=
|
||||
MAX2(devinfo->engine_class_prefetch[INTEL_ENGINE_CLASS_RENDER],
|
||||
devinfo->engine_class_prefetch[INTEL_ENGINE_CLASS_COMPUTE]);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
anv_dgc_fill_gfx_state(struct anv_dgc_gfx_state *state,
|
||||
struct anv_cmd_buffer *cmd_buffer,
|
||||
const struct anv_indirect_command_layout *layout,
|
||||
struct anv_shader ** const shaders)
|
||||
{
|
||||
struct anv_device *device = cmd_buffer->device;
|
||||
const struct vk_indirect_command_layout *vk_layout = &layout->vk;
|
||||
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
|
||||
|
||||
if (vk_layout->dgc_info & (BITFIELD_BIT(MESA_VK_DGC_PC) |
|
||||
BITFIELD_BIT(MESA_VK_DGC_SI))) {
|
||||
|
||||
for (uint32_t i = 0; i < ANV_GRAPHICS_SHADER_STAGE_COUNT; i++) {
|
||||
if (shaders[i] == NULL)
|
||||
continue;
|
||||
|
||||
const struct anv_pipeline_bind_map *bind_map = &shaders[i]->bind_map;
|
||||
for (uint32_t i = 0; i < ARRAY_SIZE(bind_map->push_ranges); i++) {
|
||||
const struct anv_push_range *range = &bind_map->push_ranges[i];
|
||||
if (range->length == 0)
|
||||
break;
|
||||
|
||||
switch (range->set) {
|
||||
case ANV_DESCRIPTOR_SET_DESCRIPTORS:
|
||||
if (bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER) {
|
||||
state->push_constants.addresses[i] =
|
||||
anv_cmd_buffer_descriptor_buffer_address(
|
||||
cmd_buffer,
|
||||
gfx->base.descriptor_buffers[range->index].buffer_index) +
|
||||
gfx->base.descriptor_buffers[range->index].buffer_offset;
|
||||
} else {
|
||||
struct anv_descriptor_set *set = gfx->base.descriptors[range->index];
|
||||
state->push_constants.addresses[i] = anv_address_physical(
|
||||
anv_descriptor_set_address(set));
|
||||
}
|
||||
break;
|
||||
|
||||
case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS:
|
||||
break;
|
||||
|
||||
case ANV_DESCRIPTOR_SET_NULL:
|
||||
case ANV_DESCRIPTOR_SET_PER_PRIM_PADDING:
|
||||
state->push_constants.addresses[i] =
|
||||
anv_address_physical(device->workaround_address);
|
||||
break;
|
||||
|
||||
default: {
|
||||
struct anv_descriptor_set *set = gfx->base.descriptors[range->set];
|
||||
const struct anv_descriptor *desc =
|
||||
&set->descriptors[range->index];
|
||||
|
||||
if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
|
||||
if (desc->buffer) {
|
||||
state->push_constants.addresses[i] = anv_address_physical(
|
||||
anv_address_add(desc->buffer->address,
|
||||
desc->offset));
|
||||
}
|
||||
} else {
|
||||
assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
|
||||
if (desc->buffer) {
|
||||
const struct anv_cmd_pipeline_state *pipe_state = &gfx->base;
|
||||
uint32_t dynamic_offset =
|
||||
pipe_state->dynamic_offsets[
|
||||
range->set].offsets[range->dynamic_offset_index];
|
||||
state->push_constants.addresses[i] = anv_address_physical(
|
||||
anv_address_add(desc->buffer->address,
|
||||
desc->offset + dynamic_offset));
|
||||
}
|
||||
}
|
||||
|
||||
if (state->push_constants.addresses[i] == 0) {
|
||||
/* For NULL UBOs, we just return an address in the
|
||||
* workaround BO. We do writes to it for workarounds but
|
||||
* always at the bottom. The higher bytes should be all
|
||||
* zeros.
|
||||
*/
|
||||
assert(range->length * 32 <= 2048);
|
||||
state->push_constants.addresses[i] =
|
||||
anv_address_physical((struct anv_address) {
|
||||
.bo = device->workaround_bo,
|
||||
.offset = 1024,
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
state->draw.instance_multiplier = gfx->instance_multiplier;
|
||||
}
|
||||
|
||||
/* This function determines the final layout of GFX generated commands. A lot
|
||||
* of things make the amount of space vary (number of stages, number of push
|
||||
* constant slots, etc...) such that we can only determine this just before
|
||||
* executing the generation.
|
||||
*/
|
||||
uint32_t
|
||||
anv_dgc_fill_gfx_layout(struct anv_dgc_gfx_layout *layout,
|
||||
const struct anv_device *device,
|
||||
const struct anv_indirect_command_layout *layout_obj,
|
||||
struct anv_shader ** const shaders)
|
||||
{
|
||||
const struct vk_indirect_command_layout *vk_layout = &layout_obj->vk;
|
||||
const struct intel_device_info *devinfo = device->info;
|
||||
|
||||
uint32_t cmd_offset = 0;
|
||||
|
||||
layout->draw.draw_type =
|
||||
(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) ? ANV_DGC_DRAW_TYPE_MESH :
|
||||
(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_INDEXED)) ? ANV_DGC_DRAW_TYPE_INDEXED :
|
||||
ANV_DGC_DRAW_TYPE_SEQUENTIAL;
|
||||
|
||||
layout->index_buffer.cmd_offset = cmd_offset;
|
||||
if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IB)) {
|
||||
layout->index_buffer.cmd_size = _3DSTATE_INDEX_BUFFER_length(devinfo) * 4;
|
||||
layout->index_buffer.seq_offset = vk_layout->index_src_offset_B;
|
||||
layout->index_buffer.mocs =
|
||||
isl_mocs(&device->isl_dev, ISL_SURF_USAGE_INDEX_BUFFER_BIT, false);
|
||||
if (vk_layout->index_mode_is_dx) {
|
||||
/* DXGI_FORMAT values */
|
||||
layout->index_buffer.u32_value = 42;
|
||||
layout->index_buffer.u16_value = 57;
|
||||
layout->index_buffer.u8_value = 62;
|
||||
} else {
|
||||
layout->index_buffer.u32_value = VK_INDEX_TYPE_UINT32;
|
||||
layout->index_buffer.u16_value = VK_INDEX_TYPE_UINT16;
|
||||
layout->index_buffer.u8_value = VK_INDEX_TYPE_UINT8_EXT;
|
||||
}
|
||||
|
||||
cmd_offset += layout->index_buffer.cmd_size;
|
||||
}
|
||||
|
||||
layout->vertex_buffers.cmd_offset = cmd_offset;
|
||||
if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_VB)) {
|
||||
layout->vertex_buffers.cmd_size =
|
||||
(1 /* TODO: _3DSTATE_VERTEX_BUFFERS_length(devinfo) */ +
|
||||
util_bitcount(vk_layout->vertex_bindings) *
|
||||
VERTEX_BUFFER_STATE_length(devinfo)) * 4;
|
||||
layout->vertex_buffers.mocs =
|
||||
isl_mocs(&device->isl_dev, ISL_SURF_USAGE_VERTEX_BUFFER_BIT, false);
|
||||
layout->vertex_buffers.n_buffers = vk_layout->n_vb_layouts;
|
||||
for (uint32_t i = 0; i < vk_layout->n_vb_layouts; i++) {
|
||||
layout->vertex_buffers.buffers[i].seq_offset =
|
||||
vk_layout->vb_layouts[i].src_offset_B;
|
||||
layout->vertex_buffers.buffers[i].binding =
|
||||
vk_layout->vb_layouts[i].binding;
|
||||
}
|
||||
|
||||
cmd_offset += layout->vertex_buffers.cmd_size;
|
||||
}
|
||||
|
||||
layout->indirect_set.final_cmds_offset = cmd_offset;
|
||||
if (intel_needs_workaround(devinfo, 16011107343) &&
|
||||
shaders[MESA_SHADER_TESS_CTRL] != NULL) {
|
||||
layout->indirect_set.final_cmds_size +=
|
||||
_3DSTATE_HS_length(devinfo) * 4;
|
||||
}
|
||||
if (intel_needs_workaround(devinfo, 22018402687) &&
|
||||
shaders[MESA_SHADER_TESS_EVAL] != NULL) {
|
||||
layout->indirect_set.final_cmds_size +=
|
||||
_3DSTATE_DS_length(devinfo) * 4;
|
||||
}
|
||||
cmd_offset += layout->indirect_set.final_cmds_size;
|
||||
|
||||
layout->push_constants.cmd_offset = cmd_offset;
|
||||
if (vk_layout->dgc_info & (BITFIELD_BIT(MESA_VK_DGC_PC) |
|
||||
BITFIELD_BIT(MESA_VK_DGC_SI))) {
|
||||
struct anv_dgc_push_layout *pc_layout = &layout->push_constants;
|
||||
|
||||
layout->push_constants.flags = ANV_DGC_PUSH_CONSTANTS_CMD_ACTIVE;
|
||||
for (uint32_t i = 0; i < vk_layout->n_pc_layouts; i++) {
|
||||
const struct vk_indirect_command_push_constant_layout *vk_pc_layout =
|
||||
&vk_layout->pc_layouts[i];
|
||||
push_layout_add_range(&layout->push_constants, vk_pc_layout);
|
||||
}
|
||||
if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_SI)) {
|
||||
pc_layout->seq_id_active = true;
|
||||
pc_layout->seq_id_offset = vk_layout->si_layout.dst_offset_B;
|
||||
}
|
||||
pc_layout->mocs =
|
||||
isl_mocs(&device->isl_dev, ISL_SURF_USAGE_CONSTANT_BUFFER_BIT, false);
|
||||
|
||||
|
||||
for (uint32_t i = 0; i < ANV_GRAPHICS_SHADER_STAGE_COUNT; i++) {
|
||||
if (shaders[i] == NULL)
|
||||
continue;
|
||||
|
||||
const struct anv_pipeline_bind_map *bind_map =
|
||||
&shaders[i]->bind_map;
|
||||
uint32_t n_slots = bind_map->inline_dwords_count > 0 ? 1 : 0;
|
||||
for (uint32_t j = 0; j < ARRAY_SIZE(bind_map->push_ranges); j++) {
|
||||
if (bind_map->push_ranges[j].length == 0)
|
||||
break;
|
||||
n_slots++;
|
||||
}
|
||||
if (n_slots > 0) {
|
||||
layout->push_constants.cmd_size +=
|
||||
push_constant_command_size(devinfo, i, n_slots);
|
||||
}
|
||||
}
|
||||
|
||||
cmd_offset += layout->push_constants.cmd_size;
|
||||
}
|
||||
|
||||
layout->draw.cmd_offset = cmd_offset;
|
||||
layout->draw.cmd_size = draw_cmd_size(devinfo, vk_layout);
|
||||
layout->draw.seq_offset = vk_layout->draw_src_offset_B;
|
||||
|
||||
cmd_offset += layout->draw.cmd_size;
|
||||
|
||||
assert(cmd_offset <= layout_obj->cmd_size);
|
||||
|
||||
return cmd_offset;
|
||||
}
|
||||
|
||||
void
|
||||
anv_dgc_print_gfx_state(FILE *f,
|
||||
const struct anv_dgc_gfx_layout *layout,
|
||||
const struct anv_indirect_command_layout *layout_obj)
|
||||
{
|
||||
fprintf(f, "Generated Gfx state:\n");
|
||||
#define PRINT(state_bits, cond2, ...) do { \
|
||||
if ((state_bits) == 0 || \
|
||||
(layout_obj->vk.dgc_info & (state_bits)) || \
|
||||
(cond2)) \
|
||||
fprintf(f, __VA_ARGS__); \
|
||||
} while (0)
|
||||
PRINT(BITFIELD_BIT(MESA_VK_DGC_IB), false,
|
||||
" ib: cmd_offset=0x%04x-0x%04x (%u)\n",
|
||||
layout->index_buffer.cmd_offset,
|
||||
layout->index_buffer.cmd_offset +
|
||||
layout->index_buffer.cmd_size,
|
||||
layout->index_buffer.cmd_size);
|
||||
PRINT(BITFIELD_BIT(MESA_VK_DGC_VB), false,
|
||||
" vb: cmd_offset=0x%04x-0x%04x (%u)\n",
|
||||
layout->vertex_buffers.cmd_offset,
|
||||
layout->vertex_buffers.cmd_offset +
|
||||
layout->vertex_buffers.cmd_size,
|
||||
layout->vertex_buffers.cmd_size);
|
||||
PRINT(0, false,
|
||||
" final: cmd_offset=0x%04x-0x%04x (%u)\n",
|
||||
layout->indirect_set.final_cmds_offset,
|
||||
layout->indirect_set.final_cmds_offset +
|
||||
layout->indirect_set.final_cmds_size,
|
||||
layout->indirect_set.final_cmds_size);
|
||||
PRINT(BITFIELD_BIT(MESA_VK_DGC_PC) |
|
||||
BITFIELD_BIT(MESA_VK_DGC_SI),
|
||||
layout->push_constants.cmd_size != 0,
|
||||
" push: cmd_offset=0x%04x-0x%04x (%u)\n",
|
||||
layout->push_constants.cmd_offset,
|
||||
layout->push_constants.cmd_offset +
|
||||
layout->push_constants.cmd_size,
|
||||
layout->push_constants.cmd_size);
|
||||
PRINT(0, false,
|
||||
" draw: cmd_offset=0x%04x-0x%04x (%u)\n",
|
||||
layout->draw.cmd_offset,
|
||||
layout->draw.cmd_offset +
|
||||
layout->draw.cmd_size,
|
||||
layout->draw.cmd_size);
|
||||
#undef PRINT
|
||||
}
|
||||
|
||||
void
|
||||
anv_dgc_print_layout(FILE *f,
|
||||
const struct anv_indirect_command_layout *layout)
|
||||
{
|
||||
fprintf(f, "Generated %s layout:\n",
|
||||
layout->bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ? "Gfx" :
|
||||
layout->bind_point == VK_PIPELINE_BIND_POINT_COMPUTE ? "CS" :
|
||||
layout->bind_point == VK_PIPELINE_BIND_POINT_COMPUTE ? "RT" : "unknown");
|
||||
#define DGC_BIT(name) ((layout->vk.dgc_info & BITFIELD_BIT(MESA_VK_DGC_##name)) ? #name"," : "")
|
||||
fprintf(f, " bits: %s%s%s%s%s%s%s%s%s%s\n",
|
||||
DGC_BIT(IES),
|
||||
DGC_BIT(PC),
|
||||
DGC_BIT(IB),
|
||||
DGC_BIT(VB),
|
||||
DGC_BIT(SI),
|
||||
DGC_BIT(DRAW),
|
||||
DGC_BIT(DRAW_INDEXED),
|
||||
DGC_BIT(DRAW_MESH),
|
||||
DGC_BIT(DISPATCH),
|
||||
DGC_BIT(RT));
|
||||
#undef DGC_BIT
|
||||
fprintf(f, " seq_stride: %zu\n", layout->vk.stride);
|
||||
fprintf(f, " cmd_prolog: %u\n", layout->cmd_prolog_size);
|
||||
fprintf(f, " cmd_stride: %u\n", layout->cmd_size);
|
||||
fprintf(f, " cmd_epilog: %u\n", layout->cmd_epilog_size);
|
||||
fprintf(f, " data_prolog: %u\n", layout->data_prolog_size);
|
||||
fprintf(f, " data_stride: %u\n", layout->data_size);
|
||||
|
||||
fprintf(f, " sequences:\n");
|
||||
const struct vk_indirect_command_layout *vk_layout = &layout->vk;
|
||||
const struct anv_dgc_push_layout *pc_layout =
|
||||
layout->bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ?
|
||||
&layout->gfx_layout.push_constants : &layout->cs_layout.push_constants;
|
||||
if (pc_layout->num_entries > 0 || pc_layout->seq_id_active) {
|
||||
fprintf(f, " push_constants:\n");
|
||||
for (uint32_t i = 0; i < pc_layout->num_entries; i++) {
|
||||
fprintf(f,
|
||||
" pc_entry%02u seq_offset: 0x%04x (offset=%hu, size=%hu)\n",
|
||||
i,
|
||||
pc_layout->entries[i].seq_offset,
|
||||
pc_layout->entries[i].push_offset,
|
||||
pc_layout->entries[i].size);
|
||||
}
|
||||
if (pc_layout->seq_id_active) {
|
||||
fprintf(f, " seq_id_offset: 0x%04hx\n",
|
||||
pc_layout->seq_id_offset);
|
||||
}
|
||||
}
|
||||
switch (layout->bind_point) {
|
||||
case VK_PIPELINE_BIND_POINT_GRAPHICS: {
|
||||
if (vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_IB)) {
|
||||
fprintf(f, " index_buffer:\n");
|
||||
fprintf(f, " seq_offset: 0x%04x\n", vk_layout->index_src_offset_B);
|
||||
}
|
||||
if (vk_layout->n_vb_layouts) {
|
||||
fprintf(f, " vertex_buffers:\n");
|
||||
for (uint32_t i = 0; i < vk_layout->n_vb_layouts; i++) {
|
||||
fprintf(f, " seq_offset: 0x%04x (vb%u)\n",
|
||||
vk_layout->vb_layouts[i].src_offset_B,
|
||||
vk_layout->vb_layouts[i].binding);
|
||||
}
|
||||
}
|
||||
fprintf(f, " %s:\n",
|
||||
(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) ? "mesh" :
|
||||
(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_INDEXED)) ? "draw-indexed" :
|
||||
(vk_layout->dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW)) ? "draw" :
|
||||
"unknown");
|
||||
fprintf(f, " seq_offset: 0x%04x\n", vk_layout->draw_src_offset_B);
|
||||
break;
|
||||
}
|
||||
case VK_PIPELINE_BIND_POINT_COMPUTE:
|
||||
case VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR: {
|
||||
const struct anv_dgc_cs_layout *cs_layout = &layout->cs_layout;
|
||||
if (cs_layout->indirect_set.active) {
|
||||
fprintf(f, " ies:\n");
|
||||
fprintf(f, " seq_offset: 0x%04x\n", cs_layout->indirect_set.seq_offset);
|
||||
}
|
||||
fprintf(f, " dispatch:\n");
|
||||
fprintf(f, " seq_offset: 0x%04x\n", cs_layout->dispatch.seq_offset);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE("Invalid bind point");
|
||||
}
|
||||
|
||||
fprintf(f, " commands:\n");
|
||||
for (uint32_t i = 0; i < layout->n_items; i++) {
|
||||
fprintf(f, " %s: %u\n",
|
||||
layout->items[i].name, layout->items[i].size);
|
||||
}
|
||||
}
|
||||
|
|
@ -87,6 +87,7 @@
|
|||
#include "vk_descriptor_set_layout.h"
|
||||
#include "vk_descriptor_update_template.h"
|
||||
#include "vk_device.h"
|
||||
#include "vk_device_generated_commands.h"
|
||||
#include "vk_device_memory.h"
|
||||
#include "vk_drm_syncobj.h"
|
||||
#include "vk_enum_defines.h"
|
||||
|
|
@ -6579,6 +6580,75 @@ enum anv_dgc_stage anv_vk_stage_to_dgc_stage(VkShaderStageFlags vk_stage);
|
|||
|
||||
uint32_t anv_vk_stages_to_generated_stages(VkShaderStageFlags vk_stages);
|
||||
|
||||
struct anv_indirect_command_layout {
|
||||
struct vk_indirect_command_layout vk;
|
||||
|
||||
VkPipelineBindPoint bind_point;
|
||||
|
||||
struct anv_dgc_gfx_layout gfx_layout;
|
||||
struct anv_dgc_cs_layout cs_layout;
|
||||
|
||||
/** Layout is as follow :
|
||||
* --------------------
|
||||
* | prolog cmds |
|
||||
* |------------------|
|
||||
* | sequence cmds |
|
||||
* |------------------|
|
||||
* | epilog cmds |
|
||||
* |------------------|
|
||||
* | sideband data |
|
||||
* |------------------|
|
||||
* | prolog data |
|
||||
* |------------------|
|
||||
* | sequence data |
|
||||
* --------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* Non sequence related commands at the beginning of the preprocess buffer
|
||||
*/
|
||||
uint32_t cmd_prolog_size;
|
||||
/**
|
||||
* Non sequence related commands at the end of the preprocess buffer (jump
|
||||
* back to main batch)
|
||||
*/
|
||||
uint32_t cmd_epilog_size;
|
||||
/** Amount of command memory required for each sequence */
|
||||
uint32_t cmd_size;
|
||||
/** Non sequence related data */
|
||||
uint32_t data_prolog_size;
|
||||
/** Amount of data memory required (per sequence) */
|
||||
uint32_t data_size;
|
||||
/** Amount of sideband data memory required (not per sequence) */
|
||||
uint32_t sideband_size;
|
||||
|
||||
/** Track if push constants are emitted at all */
|
||||
bool emits_push_constants;
|
||||
|
||||
struct anv_indirect_command_layout_item {
|
||||
const char *name;
|
||||
uint32_t size;
|
||||
} items[10];
|
||||
uint32_t n_items;
|
||||
};
|
||||
|
||||
void anv_dgc_print_gfx_state(FILE *f,
|
||||
const struct anv_dgc_gfx_layout *layout,
|
||||
const struct anv_indirect_command_layout *layout_obj);
|
||||
void anv_dgc_print_layout(FILE *f,
|
||||
const struct anv_indirect_command_layout *layout);
|
||||
|
||||
void anv_dgc_fill_gfx_state(struct anv_dgc_gfx_state *state,
|
||||
struct anv_cmd_buffer *cmd_buffer,
|
||||
const struct anv_indirect_command_layout *layout_obj,
|
||||
struct anv_shader ** const shaders);
|
||||
|
||||
uint32_t anv_dgc_fill_gfx_layout(struct anv_dgc_gfx_layout *layout,
|
||||
const struct anv_device *device,
|
||||
const struct anv_indirect_command_layout *layout_obj,
|
||||
struct anv_shader ** const shaders);
|
||||
|
||||
|
||||
struct anv_vid_mem {
|
||||
struct anv_device_memory *mem;
|
||||
VkDeviceSize offset;
|
||||
|
|
@ -6989,6 +7059,9 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(anv_performance_configuration_intel, base,
|
|||
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_video_session, vk.base,
|
||||
VkVideoSessionKHR,
|
||||
VK_OBJECT_TYPE_VIDEO_SESSION_KHR)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_indirect_command_layout, vk.base,
|
||||
VkIndirectCommandsLayoutEXT,
|
||||
VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_EXT)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_indirect_execution_set, base,
|
||||
VkIndirectExecutionSetEXT,
|
||||
VK_OBJECT_TYPE_INDIRECT_EXECUTION_SET_EXT)
|
||||
|
|
|
|||
|
|
@ -160,6 +160,7 @@ libanv_files = files(
|
|||
'anv_cmd_buffer.c',
|
||||
'anv_descriptor_set.c',
|
||||
'anv_device.c',
|
||||
'anv_dgc_layout.c',
|
||||
'anv_dgc_set.c',
|
||||
'anv_embedded_sampler.c',
|
||||
'anv_event.c',
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue