anv: implement generated preprocess & execute

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31384>

src/intel/vulkan/anv_private.h

@@ -4639,6 +4639,11 @@ enum anv_color_aux_op_class {
    ANV_COLOR_AUX_OP_CLASS_SW_RESOLVE,
 };
 
+enum anv_dgc_state {
+   ANV_DGC_STATE_COMPUTE = BITFIELD_BIT(0),
+   ANV_DGC_STATE_GRAPHIC = BITFIELD_BIT(1),
+};
+
 /** State required while building cmd buffer */
 struct anv_cmd_state {
    /* PIPELINE_SELECT.PipelineSelection */
@@ -4731,6 +4736,12 @@ struct anv_cmd_state {
    unsigned char                                surface_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
    unsigned char                                push_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
 
+   /**
+    * DGC states .
+    */
+   enum anv_dgc_state                           dgc_states;
+   bool                                         has_dgc;
+
    /* The last auxiliary surface operation (or equivalent operation) provided
     * to genX(cmd_buffer_update_color_aux_op).
     */
@@ -5035,6 +5046,14 @@ anv_cmd_buffer_has_gfx_stage(struct anv_cmd_buffer *cmd_buffer,
    return cmd_buffer->state.gfx.shaders[stage] != NULL;
 }
 
+#define anv_internal_kernel_variant(cmd_buffer, name) ({                \
+         ((anv_cmd_buffer_is_compute_queue(cmd_buffer) ||               \
+           (cmd_buffer)->state.current_pipeline ==                      \
+           (cmd_buffer)->device->physical->gpgpu_pipeline_value) ?      \
+          ANV_INTERNAL_KERNEL_##name##_COMPUTE :                        \
+          ANV_INTERNAL_KERNEL_##name##_FRAGMENT);                       \
+      })
+
 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);

src/intel/vulkan/genX_cmd_buffer.c

@@ -4090,8 +4090,41 @@ emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
    }
 }
 
+static void
+reset_dgc_state(struct anv_cmd_buffer *cmd_buffer)
+{
+   if (cmd_buffer->state.dgc_states == 0)
+      return;
+
+#if GFX_VERx10 <= 120
+   if (cmd_buffer->state.dgc_states & ANV_DGC_STATE_COMPUTE) {
+      struct anv_state state =
+         anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
+                                            GENX(INTERFACE_DESCRIPTOR_DATA_length) * 4, 64);
+
+      struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
+         .NumberofThreadsinGPGPUThreadGroup = 1,
+      };
+      GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL, state.map, &desc);
+
+      anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_VFE_STATE), vfe) {
+         vfe.MaximumNumberofThreads = 1;
+         vfe.NumberofURBEntries = 1;
+      }
+      anv_batch_emit(&cmd_buffer->batch,
+                     GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
+         mid.InterfaceDescriptorTotalLength        = state.alloc_size;
+         mid.InterfaceDescriptorDataStartAddress   = state.offset;
+      }
+   }
+#endif
+
+   cmd_buffer->state.dgc_states = 0;
+}
+
 static VkResult
-end_command_buffer(struct anv_cmd_buffer *cmd_buffer)
+end_command_buffer(struct anv_cmd_buffer *cmd_buffer,
+                   bool is_companion)
 {
    if (anv_batch_has_error(&cmd_buffer->batch))
       return cmd_buffer->batch.status;
@@ -4108,22 +4141,28 @@ end_command_buffer(struct anv_cmd_buffer *cmd_buffer)
       return VK_SUCCESS;
    }
 
-   /* Flush query clears using blorp so that secondary query writes do not
-    * race with the clear.
-    */
-   if (cmd_buffer->state.queries.clear_bits) {
-      anv_add_pending_pipe_bits(cmd_buffer,
-                                VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
-                                VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
-                                ANV_PIPE_QUERY_BITS(cmd_buffer->state.queries.clear_bits),
-                                "query clear flush prior command buffer end");
-   }
-
    /* Flush any in-progress CCS/MCS operations in preparation for chaining. */
    genX(cmd_buffer_update_color_aux_op)(cmd_buffer, ANV_COLOR_AUX_OP_CLASS_NONE);
 
    genX(cmd_buffer_flush_generated_draws)(cmd_buffer);
 
+   if (!is_companion) {
+      reset_dgc_state(cmd_buffer);
+
+      /* Flush query clears using blorp so that secondary query writes do not
+       * race with the clear.
+       */
+      if (cmd_buffer->state.queries.clear_bits) {
+         anv_add_pending_pipe_bits(cmd_buffer,
+                                   VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
+                                   VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
+                                   ANV_PIPE_QUERY_BITS(cmd_buffer->state.queries.clear_bits),
+                                   "query clear flush prior command buffer end");
+      }
+
+      genX(cmd_buffer_flush_generated_draws)(cmd_buffer);
+   }
+
    /* Turn on object level preemption if it is disabled to have it in known
     * state at the beginning of new command buffer.
     */
@@ -4173,7 +4212,7 @@ genX(EndCommandBuffer)(
 {
    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   VkResult status = end_command_buffer(cmd_buffer);
+   VkResult status = end_command_buffer(cmd_buffer, false);
    if (status != VK_SUCCESS)
       return status;
 
@@ -4183,7 +4222,7 @@ genX(EndCommandBuffer)(
    if (cmd_buffer->companion_rcs_cmd_buffer) {
        assert(anv_cmd_buffer_is_compute_queue(cmd_buffer) ||
               anv_cmd_buffer_is_blitter_queue(cmd_buffer));
-       status = end_command_buffer(cmd_buffer->companion_rcs_cmd_buffer);
+       status = end_command_buffer(cmd_buffer->companion_rcs_cmd_buffer, true);
    }
 
    ANV_RMV(cmd_buffer_create, cmd_buffer->device, cmd_buffer);
@@ -5495,6 +5534,8 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
        (GFX_VERx10 != 125 || cmd_buffer->state.current_pipeline_systolic == uses_systolic))
       return;
 
+   reset_dgc_state(cmd_buffer);
+
 #if GFX_VER < 20
 #if GFX_VER == 9
    /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:

src/intel/vulkan/meson.build

@@ -90,6 +90,7 @@ anv_per_hw_ver_files = files(
   'genX_blorp_exec.c',
   'genX_cmd_buffer.c',
   'genX_cmd_compute.c',
+  'genX_cmd_dgc.c',
   'genX_cmd_draw.c',
   'genX_cmd_draw_generated_flush.h',
   'genX_cmd_draw_generated_indirect.h',