Commit graph

221211 commits

Author SHA1 Message Date
Lorenzo Rossi
83fd45aa5a pan/compiler: Fix noperspective int varyings
Ints and floats do not need to match between VS and FS, some crazy
shaders might write an uint from the VS and read a noperspective float
from the FS.  There will be new tests in the conformance tests that
check that too shortly.

Is this a performance regression? yes.
Can we fix this easily? No, we'll need dynamic prolog/epilog linking.

Since maybe_noperspective is almost useless after this fix, the whole
logic has been removed

Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40844>
2026-04-15 10:32:18 +00:00
Lorenzo Rossi
6e67f2a996 pan/compiler: Don't crash nopersp if pos is undefined
VS does not need to write the position, it can also leave it as
undefined.  We agree that there isn't much sense in noperspective
varyings with undefined perspective, but we still do not want to crash.
This does lead to some real crashes if we mistake some int varying to
noperspective (see next commit).

Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40844>
2026-04-15 10:32:18 +00:00
Georg Lehmann
5607417f57 radv: remove radv_nir_lower_viewport_to_zero
Some checks are pending
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nir_opt_varyings does this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:17:01 +00:00
Georg Lehmann
c842186e39 radv: remove lower array vars to elem
No Foz-DB changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:17:01 +00:00
Georg Lehmann
c7a953809a radv: don't lower io vars to scalar
Done later on lowered IO.

Foz-DB Navi48:
Totals from 4 (0.00% of 205045) affected shaders:
Instrs: 1434 -> 1418 (-1.12%)
CodeSize: 7912 -> 7848 (-0.81%)
Latency: 5688 -> 5646 (-0.74%)
InvThroughput: 642 -> 646 (+0.62%)
PreVGPRs: 104 -> 100 (-3.85%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:17:01 +00:00
Georg Lehmann
b2e59d80b0 radv: do not shrink vectors when lowering IO vars to scalar
I wanted to move this later, but looking at the stats, this pass
actually hurts here because it shrinks smem loads that would be better
vectorized. So just remove it.

Foz-DB Navi48:
Totals from 2268 (1.11% of 205045) affected shaders:
Instrs: 1573491 -> 1569535 (-0.25%); split: -0.35%, +0.10%
CodeSize: 8399092 -> 8378632 (-0.24%); split: -0.39%, +0.14%
SpillSGPRs: 312 -> 355 (+13.78%)
Latency: 12223349 -> 12225239 (+0.02%); split: -0.20%, +0.21%
InvThroughput: 2235646 -> 2236174 (+0.02%); split: -0.15%, +0.17%
VClause: 26526 -> 26549 (+0.09%); split: -0.02%, +0.11%
SClause: 34974 -> 34053 (-2.63%); split: -3.01%, +0.37%
Copies: 114417 -> 115513 (+0.96%); split: -0.33%, +1.28%
Branches: 28085 -> 26899 (-4.22%); split: -4.24%, +0.02%
PreSGPRs: 98109 -> 99024 (+0.93%); split: -0.10%, +1.03%
PreVGPRs: 78224 -> 78226 (+0.00%)
VALU: 929067 -> 928588 (-0.05%); split: -0.08%, +0.03%
SALU: 204756 -> 206936 (+1.06%); split: -0.19%, +1.26%
SMEM: 67181 -> 64687 (-3.71%); split: -3.83%, +0.11%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:17:00 +00:00
Georg Lehmann
f001afad23 radv: remove some unneeded passes from radv_nir_lower_io_vars_to_scalar
No Foz-DB changes on Navi48.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:16:59 +00:00
Georg Lehmann
e0883d107a radv: do not remove dead variables
No Foz-DB changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:16:59 +00:00
Georg Lehmann
8c98ed9e85 radv: do not vectorize io variables
No Foz-DB changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:16:59 +00:00
Georg Lehmann
d14fc27f44 radv: do not vectorize fs out variables
This is scalarized later anyway.

No Foz-DB changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:16:58 +00:00
Georg Lehmann
5d8c817fd7 radv: lower lowered io to scalar
We already did this for everything except
fragment shader outputs with epilogs.

If we move it a bit earlier, we can stop lowering IO
variables to scalar.

Foz-DB Navi48:
Totals from 1001 (0.49% of 205045) affected shaders:
MaxWaves: 31252 -> 31256 (+0.01%)
Instrs: 372258 -> 372036 (-0.06%); split: -0.14%, +0.08%
CodeSize: 1999064 -> 1997836 (-0.06%); split: -0.13%, +0.06%
VGPRs: 39096 -> 39072 (-0.06%)
Latency: 1235558 -> 1235435 (-0.01%); split: -0.08%, +0.07%
InvThroughput: 213845 -> 213875 (+0.01%); split: -0.06%, +0.07%
VClause: 5840 -> 5838 (-0.03%)
SClause: 10964 -> 10969 (+0.05%); split: -0.03%, +0.07%
Copies: 21469 -> 21545 (+0.35%); split: -0.42%, +0.78%
Branches: 5326 -> 5324 (-0.04%)
PreSGPRs: 34214 -> 34206 (-0.02%); split: -0.03%, +0.01%
PreVGPRs: 21931 -> 22001 (+0.32%); split: -0.06%, +0.38%
VALU: 212386 -> 212418 (+0.02%); split: -0.07%, +0.09%
SALU: 50409 -> 50378 (-0.06%); split: -0.07%, +0.01%
VMEM: 8352 -> 8331 (-0.25%)
SMEM: 17966 -> 17963 (-0.02%)

This is mostly RA noise in GPL FS shaders.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
2026-04-15 09:16:58 +00:00
Natalie Vock
1f998b38f4 radv: Run nir_opt_deref after first optimization loop
Only at this point are loads from uninitialized variables lowered to
undef and copy-propagated so that nir_opt_deref's cast-of-undef
optimization works properly.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40799>
2026-04-15 08:42:12 +00:00
Natalie Vock
57f796752d nir/deref: Elide loads/stores from deref cast of undef
These can never be meaningful. DOOM: The Dark Ages also relies on this.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40799>
2026-04-15 08:42:12 +00:00
Job Noorman
118b975ce7 ir3: use ldg.k load size
Some checks are pending
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ldg.k can copy up to 256 vec4s at once but we currently emit one ldg.k
per vec4. Fix this by using the load size field of ldg.k.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:01 +00:00
Job Noorman
a1272cabe0 ir3/isa: fix load size encoding for ldg.k
The load size field starts at b23 instead of b24 and is 8 bits in size.
b23 makes the blob disassembler select between interpreting the load
size as an immediate or a GPR. However, using a GPR doesn't work as the
HW still seems to interpret the field as an immediate. We copy the
blob's behavior here for consistency.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:01 +00:00
Job Noorman
e6529b54c0 ir3: add support for the ldg.k a1.x addressing mode
We assumed a1.x addressing doesn't work. However, it turns out it
actually does work but instead of taking the offset's hight bits from
a1.x and adding an immediate to the low bits, the full offset is stored
in a1.x and the offset is ignored.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:01 +00:00
Job Noorman
bf167ca73b ir3: allow shared address src for ldg.k
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:00 +00:00
Christoph Pillmayer
3427b20b71 pan/bi: Fix MEMMOV size calculation
Doing stores first, loads second doesn't work because there can be
chains of store, load, store... .
Use a fixed point approach instead to calculate sizes for all
destinations.

Fixes: 2fd5b8a391 ("pan/bi: Account for MEMMOV in bi_record_sizes")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40915>
2026-04-15 07:22:35 +00:00
Job Noorman
ce810bb19b ir3/parser: add @constlen header
Constlen cannot always be derived from the usage of @const et al. For
example when using ldc.k/ldg.k. Add a @constlen header to explicitly set
it.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40940>
2026-04-15 06:46:10 +00:00
Job Noorman
0e95730be0 ir3/parser: set constlen when adding const regs
Since we don't set constlen anymore based on static const reg usage,
computerator was broken. Fix this by setting constlen for @const et al.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 4e456ebde4 ("ir3/collect_info: remove max_const calculation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40940>
2026-04-15 06:46:09 +00:00
Job Noorman
4808037f6e ir3/legalize: track need_ss/sy_for_const per const reg
Instead of tracking if *any* const reg has been written since the last
sync, use a bitset to track exactly which const regs have been written.
This often helps us prevent stalls.

Preamble stats:

Totals from 32893 (18.66% of 176258) affected shaders:
Instrs: 3540796 -> 3540370 (-0.01%); split: -0.08%, +0.07%
CodeSize: 30635588 -> 30627370 (-0.03%); split: -0.09%, +0.07%
NOPs: 491600 -> 491174 (-0.09%); split: -0.58%, +0.49%
(ss): 465746 -> 450057 (-3.37%); split: -3.54%, +0.17%
(sy): 89251 -> 85497 (-4.21%); split: -4.30%, +0.09%
(ss)-stall: 1210233 -> 1164381 (-3.79%); split: -4.44%, +0.66%
(sy)-stall: 1286176 -> 1283034 (-0.24%); split: -0.94%, +0.70%
Cat0: 594508 -> 594082 (-0.07%); split: -0.48%, +0.41%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40954>
2026-04-15 06:20:56 +00:00
Job Noorman
c1bf9d6fd5 ir3: set cat6.dst_offset for ldc
Not needed by the assembler but this allows us to track the const reg
destination in ir3.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40954>
2026-04-15 06:20:56 +00:00
Job Noorman
b730dff54e ir3/postsched: update legalize state for terminators
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Terminators might need sync flags/delays and hence have an effect on
scheduling decisions.

Totals from 13218 (7.50% of 176258) affected shaders:
Instrs: 12241764 -> 12237098 (-0.04%); split: -0.14%, +0.10%
CodeSize: 23483966 -> 23479174 (-0.02%); split: -0.08%, +0.06%
NOPs: 2594291 -> 2589625 (-0.18%); split: -0.67%, +0.49%
(ss): 381711 -> 381252 (-0.12%); split: -0.41%, +0.29%
(sy): 167625 -> 165596 (-1.21%); split: -1.21%, +0.00%
(ss)-stall: 1645060 -> 1615134 (-1.82%); split: -2.11%, +0.29%
(sy)-stall: 4920750 -> 4835994 (-1.72%); split: -1.89%, +0.17%
Preamble Instrs: 2478730 -> 2478732 (+0.00%); split: -0.00%, +0.00%
Cat0: 2881982 -> 2877316 (-0.16%); split: -0.60%, +0.44%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40952>
2026-04-15 05:57:17 +00:00
Vinson Lee
5982deb48b zink: remove unused variable in zink_instance.py
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
src/gallium/drivers/zink/zink_instance.c:34:9: warning: variable 'have_moltenvk_layer' set but not used [-Wunused-but-set-variable]

Fixes: 2b4fcf0a06 ("zink: generate instance creation code with a python script")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40910>
2026-04-14 23:44:45 +00:00
Mauro Rossi
cc44922048 intel/jay: fix static_assert expression
Some checks are pending
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Fixes the following building error:

FAILED: src/intel/compiler/jay/libintel_compiler_jay.a.p/jay_assign_flags.c.o
...
In file included from ../src/intel/compiler/jay/jay_assign_flags.c:6:
../src/intel/compiler/jay/jay_builder.h:184:24: error: static_assert expression is not an integral constant expression
         static_assert(sizeof(uintptr_t) <= sizeof(uint64_t) &&
                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Fixes: e42e3193 ("intel: add Jay")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
1b029f3279 jay: allow cmod on cvt
it's just a MOV

saves an instruction on dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_8

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
9df62df55e jay: fix bfn cmod
affects dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_8

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
b9f8467855 jay: fix a bunch of opcode properties
really need a full audit..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
8afcbbe77d jay: load_simd_width_intel
dEQP-GLES31.functional.shaders.arrays_of_arrays.es31.array_access.dynamic_expression_access_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
4eb838eb48 jay: split up jay_from_nir.c
Big monolithic file, split it up into the relevant pieces.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
6925d9ee23 jay: move deswizzle hack outside of swsb
this will eventually enable better swsb for the simd32 payload code.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
48a24f3c27 jay: fix instr counts
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Kenneth Graunke
3a1227f36b jay: Clear default group for quad swizzles
Quad swizzles should always execute with NoMask and group 0.

We skipped initializing the group, and so inherited whatever the state
from the previous instruction was.  This led to incorrect behavior if
the previous instruction was SIMD split:

   (16)        mov.u32 g84<2>, g2        |
   (16|M16)    mov.u32 g86<2>, g3        |
   (32|M16&W)  mov.u32 g2, g126.2<4,4,0> | I@1

Oops.  The final quad swizzle shouldn't have had M16 set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Kenneth Graunke
8bfb139033 jay: Make lower_immediates bail if there are no sources
For example, JAY_OPCODE_PRELOAD has no sources.  Reading src[other]
would read uninitialized data.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Kenneth Graunke
a79931421c jay: Assert that source is not null in jay_copy_strided
Catch bugs earlier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
e84cba531b jay: fix simd split swsb bugs
this is subtle, but the relevant igc:

  // In case of shooting down of this instruction, we need to add sync to
  // preserve the swsb id sync, so that it's safe to clear the dep
  if (currInst.hasPredication() ||
      (currInst.getExecSize() != dep.getInstruction()->getExecSize()) ||
      (currInst.getChannelOffset() != dep.getInstruction()->getChannelOffset()))
    needSyncForShootDownInst = true;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
e66bfbd691 jay: fix SEND scoreboarding
by inspection in a glmark2 shader.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
10fbfe1f65 jay: improve vector affinities
Totals:
Instrs: 2807558 -> 2805545 (-0.07%); split: -0.10%, +0.02%
CodeSize: 45051504 -> 45015888 (-0.08%); split: -0.11%, +0.03%

Totals from 631 (23.84% of 2647) affected shaders:
Instrs: 736113 -> 734100 (-0.27%); split: -0.37%, +0.10%
CodeSize: 11666608 -> 11630992 (-0.31%); split: -0.42%, +0.12%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
dd6efffb47 jay: generalize alignment heuristic
Totals:
Instrs: 2807560 -> 2805375 (-0.08%); split: -0.27%, +0.20%
CodeSize: 45051536 -> 45011488 (-0.09%); split: -0.28%, +0.19%

Totals from 1292 (48.81% of 2647) affected shaders:
Instrs: 2154123 -> 2151938 (-0.10%); split: -0.36%, +0.26%
CodeSize: 34658096 -> 34618048 (-0.12%); split: -0.36%, +0.25%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
e54898fdc8 jay: tweak roundrobin
Totals:
Instrs: 2809726 -> 2807560 (-0.08%); split: -0.39%, +0.31%
CodeSize: 45085472 -> 45051536 (-0.08%); split: -0.41%, +0.33%

Totals from 2229 (84.21% of 2647) affected shaders:
Instrs: 2726162 -> 2723996 (-0.08%); split: -0.40%, +0.32%
CodeSize: 43775120 -> 43741184 (-0.08%); split: -0.42%, +0.34%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
8aeeaa4d85 jay: marginally improve send splitting heuristic
Instrs: 2810815 -> 2809726 (-0.04%); split: -0.07%, +0.04%
CodeSize: 45101440 -> 45085472 (-0.04%); split: -0.07%, +0.04%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
820e3a9403 jay: roundrobin RA
Totals:
Instrs: 2827788 -> 2810815 (-0.60%); split: -1.12%, +0.52%
CodeSize: 45449488 -> 45101440 (-0.77%); split: -1.28%, +0.51%
Number of spill instructions: 1984 -> 1982 (-0.10%)
Number of fill instructions: 2272 -> 2270 (-0.09%)

Totals from 2449 (92.52% of 2647) affected shaders:
Instrs: 2818824 -> 2801851 (-0.60%); split: -1.13%, +0.53%
CodeSize: 45314880 -> 44966832 (-0.77%); split: -1.28%, +0.51%
Number of spill instructions: 1984 -> 1982 (-0.10%)
Number of fill instructions: 2272 -> 2270 (-0.09%)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
57a00707a1 jay: drop GRF reg stats
doesn't match what brw does, will revisit for Xe3.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
4ab67f80e9 jay: rematerialize address regs
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
9a9365ff9b jay: fix W-entry calcs
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
2026-04-14 23:14:07 +00:00
Dave Airlie
7067b66846 nvk: don't set sector promotion on texture headers
This appears to cause some sort of prefetching which is causing
page faults for linear textures on the following page after the
texture allocation.

This might be okay for tiled, but for now just disable it.

The test crashing this was to allocate an 800x409 linear 2D texture
which gnome-initial-setup was doing.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15277
Cc: mesa-stable
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40939>
2026-04-14 21:56:56 +00:00
Collabora's Gfx CI Team
b247679ed8 Uprev ANGLE to 5e591d03650dd427001e355f4884b857cadab113
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
599125448d...5e591d0365

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40599>
2026-04-14 20:34:52 +00:00
Sergi Blanch Torne
8d7ab8ba6d ci: nightly run xfiles for a618 angle job
It may be related with !37802

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40599>
2026-04-14 20:34:52 +00:00
Karol Herbst
9fdf3f684f nak: uregs are 6 bits before Hopper, so enforce that
Some instructions actually use the 2 other bits for things, e.g. sust

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40891>
2026-04-14 20:18:39 +00:00
Karol Herbst
bf6c3e9d99 nak: add is_gpr_reg and is_ugpr_reg helpers
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40891>
2026-04-14 20:18:39 +00:00