fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 02:48:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

radv: remove radv_nir_lower_viewport_to_zero
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details

Browse source 
nir_opt_varyings does this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40955>
This commit is contained in:
Georg Lehmann 2026-04-14 17:49:14 +02:00 • committed by Marge Bot
parent c842186e39
commit 5607417f57
4 changed files with 0 additions and 91 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/amd/vulkan/meson.build
View file

@ -76,7 +76,6 @@ libradv_files = files(
'nir/radv_nir_lower_printf.c',
'nir/radv_nir_lower_ray_queries.c',
'nir/radv_nir_lower_view_index.c',
'nir/radv_nir_lower_viewport_to_zero.c',
'nir/radv_nir_lower_vs_inputs.c',
'nir/radv_nir_opt_fs_builtins.c',
'nir/radv_nir_opt_tid_function.c',

2
src/amd/vulkan/nir/radv_nir.h
View file

@ -57,8 +57,6 @@ bool radv_nir_lower_intrinsics_early(nir_shader *nir, bool lower_view_index_to_z
bool radv_nir_lower_view_index(nir_shader *nir);
bool radv_nir_lower_viewport_to_zero(nir_shader *nir);
bool radv_nir_export_multiview(nir_shader *nir);
unsigned radv_map_io_driver_location(unsigned semantic);

32
src/amd/vulkan/nir/radv_nir_lower_viewport_to_zero.c
View file

@ -1,32 +0,0 @@
/*
* Copyright © 2016 Red Hat.
* Copyright © 2016 Bas Nieuwenhuizen
* Copyright © 2023 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#include "nir.h"
#include "nir_builder.h"
#include "radv_nir.h"
static bool
pass(nir_builder *b, nir_intrinsic_instr *intr, void *_)
{
if (intr->intrinsic != nir_intrinsic_load_deref)
return false;
nir_variable *var = nir_intrinsic_get_var(intr, 0);
if (var->data.mode != nir_var_shader_in || var->data.location != VARYING_SLOT_VIEWPORT)
return false;
b->cursor = nir_before_instr(&intr->instr);
nir_def_replace(&intr->def, nir_imm_zero(b, 1, 32));
return true;
}
bool
radv_nir_lower_viewport_to_zero(nir_shader *nir)
{
return nir_shader_intrinsics_pass(nir, pass, nir_metadata_control_flow, NULL);
}

56
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -1203,22 +1203,6 @@ merge_tess_info(struct shader_info *tes_info, struct shader_info *tcs_info)
tcs_info->tess._primitive_mode = tes_info->tess._primitive_mode;
}
static void
radv_link_shaders(struct radv_shader_stage *producer_stage, struct radv_shader_stage *consumer_stage,
const struct radv_graphics_state_key *gfx_state)
{
nir_shader *producer = producer_stage->nir;
nir_shader *consumer = consumer_stage->nir;
if (consumer->info.stage == MESA_SHADER_FRAGMENT) {
/* Lower the viewport index to zero when the last vertex stage doesn't export it. */
if ((consumer->info.inputs_read & VARYING_BIT_VIEWPORT) &&
!(producer->info.outputs_written & VARYING_BIT_VIEWPORT)) {
NIR_PASS(_, consumer, radv_nir_lower_viewport_to_zero);
}
}
}
static const mesa_shader_stage graphics_shader_order[] = {
MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, MESA_SHADER_TESS_EVAL, MESA_SHADER_GEOMETRY,
@ -1236,14 +1220,6 @@ radv_link_vs(struct radv_shader_stage *vs_stage, struct radv_shader_stage *next_
if (radv_should_export_multiview(vs_stage, gfx_state)) {
NIR_PASS(_, vs_stage->nir, radv_nir_export_multiview);
}
if (next_stage) {
assert(next_stage->nir->info.stage == MESA_SHADER_TESS_CTRL ||
next_stage->nir->info.stage == MESA_SHADER_GEOMETRY ||
next_stage->nir->info.stage == MESA_SHADER_FRAGMENT);
radv_link_shaders(vs_stage, next_stage, gfx_state);
}
}
static void
@ -1256,8 +1232,6 @@ radv_link_tcs(struct radv_shader_stage *tcs_stage, struct radv_shader_stage *tes
assert(tcs_stage->nir->info.stage == MESA_SHADER_TESS_CTRL);
assert(tes_stage->nir->info.stage == MESA_SHADER_TESS_EVAL);
radv_link_shaders(tcs_stage, tes_stage, gfx_state);
/* Copy TCS info into the TES info */
merge_tess_info(&tes_stage->nir->info, &tcs_stage->nir->info);
}
@ -1271,13 +1245,6 @@ radv_link_tes(struct radv_shader_stage *tes_stage, struct radv_shader_stage *nex
if (radv_should_export_multiview(tes_stage, gfx_state)) {
NIR_PASS(_, tes_stage->nir, radv_nir_export_multiview);
}
if (next_stage) {
assert(next_stage->nir->info.stage == MESA_SHADER_GEOMETRY ||
next_stage->nir->info.stage == MESA_SHADER_FRAGMENT);
radv_link_shaders(tes_stage, next_stage, gfx_state);
}
}
static void
@ -1289,26 +1256,6 @@ radv_link_gs(struct radv_shader_stage *gs_stage, struct radv_shader_stage *fs_st
if (radv_should_export_multiview(gs_stage, gfx_state)) {
NIR_PASS(_, gs_stage->nir, radv_nir_export_multiview);
}
if (fs_stage) {
assert(fs_stage->nir->info.stage == MESA_SHADER_FRAGMENT);
radv_link_shaders(gs_stage, fs_stage, gfx_state);
}
}
static void
radv_link_task(struct radv_shader_stage *task_stage, struct radv_shader_stage *mesh_stage,
const struct radv_graphics_state_key *gfx_state)
{
assert(task_stage->nir->info.stage == MESA_SHADER_TASK);
if (mesh_stage) {
assert(mesh_stage->nir->info.stage == MESA_SHADER_MESH);
/* Linking task and mesh shaders shouldn't do anything for now but keep it for consistency. */
radv_link_shaders(task_stage, mesh_stage, gfx_state);
}
}
static void
@ -1327,8 +1274,6 @@ radv_link_mesh(struct radv_shader_stage *mesh_stage, struct radv_shader_stage *f
var->data.per_primitive = true;
}
}
radv_link_shaders(mesh_stage, fs_stage, gfx_state);
}
/* Lower mesh shader draw ID to zero prevent app bugs from triggering undefined behaviour. */
@ -1385,7 +1330,6 @@ radv_graphics_shaders_link(const struct radv_device *device, const struct radv_g
radv_link_gs(&stages[s], next_stage, gfx_state);
break;
case MESA_SHADER_TASK:
radv_link_task(&stages[s], next_stage, gfx_state);
break;
case MESA_SHADER_MESH:
radv_link_mesh(&stages[s], next_stage, gfx_state);