Commit graph

168289 commits

Author SHA1 Message Date
Martin Roukala (né Peres)
77c3df53ae zink/ci: update the radv expectations
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:04 +00:00
Martin Roukala (né Peres)
c69e2849a6 zink/ci: increase the parallelism of zink-radv-vangogh-valve
It current takes 17 minutes to run this job, which is above the 15
minutes target for Mesa CI. Let's increase the parallelism to reduce
exec time to closer to 13 minutes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:04 +00:00
Martin Roukala (né Peres)
928aab57a3 radv/ci: reduce the parallelism for vkcts-vangogh
We are about to enable pre-merge testing for radv-zink on vangogh,
which would mean the steam decks would be used for the following jobs:

 * Mesa pre-merge CI:
  * zink: 3 (~12 minutes)
 * Mesa Post-merge CI:
   * vkcts: 4 (~30 minutes)
   * vkd3d: 1 (~5 minutes)
 * DXVK CI: 1 (takes ~4 hours)

This means we could have 9 jobs running at the same time on steam
decks, despite only having 6 available. By reducing the number of decks
allocated for VKCTS runs from 4 to 2, we get closer to the actual
availability, and since vkd3d is so short + DXVK CI runs so
infrequently, we should never have to wait for a deck for too long!

Unfortunately, with the change of parallelism, a known flake started
failing more consistently, so I added it to the flakes list.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:03 +00:00
Erik Faye-Lund
5c5c114fa2 meson: correct typo in comment
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21868>
2023-03-16 10:31:04 +00:00
Gert Wollny
3ddbf64e41 virgl: Lower binding start into buffer indices
This requires that we limit the number of max combinded SSBOs to 31,
otherwisewe shaders that use SSBO binding points with higher values
will break on the host.

Fixes CTS:
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case1
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case2
  KHR-GL43.shader_storage_buffer_object.advanced-indirectAddressing-case2
  KHR-GL43.shader_storage_buffer_object.advanced-usage-case1
  KHR-GL43.shader_storage_buffer_object.advanced-usage-sync
  KHR-GL43.shader_storage_buffer_object.advanced-matrix

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
99416624e5 ntt: add option to lower SSBO bindings to buffer index
When a shader uses SSBOs in various shader stages, then we have to track
the binding locations in order to be able to properly bind these SSBOs.

Therefore add a flag that enables adding the start index of the bindings to
the SSBO index.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
1247b23f28 virgl: Don't try to do re-alloc or readback by transfer for blob resources
Blob resources are mapped directly, no need to copy data around, and
in any case, neither the resource nor the transfer info will have an
IOV attached to it, so the transfer would result error out on the host
anyway.

In addition, blob resources should not use re-allocation.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
831e7818aa virgl: Enable AMD_vertex_shader_(layer|viewport_index) when host supports it
This increase the number of cases when the texture upload from buffer
can use the PBO upload code path.

v2: Fix logic combination (Corentin)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Constantine Shablya
d53aba56db anv: use vk_get_physical_device_features
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:29 +00:00
Alyssa Rosenzweig
ded810ded5 panvk: Use vk_get_physical_device_features
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
723825f5c7 vulkan: use vk_features for vk_device::enabled_features
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
c7300a6a3b vulkan: add hepler for vkGetPhysicalDeviceFeatures2
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
efaf3fd5fc vulkan: delete trailing namespace
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
cd35ab9570 vulkan: tidy up vk_physical_device_features
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
b0b3b9e8b1 vulkan: relocate rmv to its correct home
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Qiang Yu
51e725df29 radeonsi: monolithic TCS emit tessfactor in nir directly
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:31 +00:00
Qiang Yu
3f5d42a28a radeonsi: lower nir_load_ring_tess_factors_offset_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
719366c2b2 ac/llvm,radeonsi: lower nir_load_ring_tess_factors_amd
No one implement this intrinsic in llvm, so remove the
llvm entry too.

This will be used in TCS nir tess factor write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
99828e0390 ac/nir: handle tess factor output missing case
tcs_tess_lvl_(in|out)_loc may be not set if user miss tess
factor output.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
700e24941c ac/nir: init tess factor location with IO remap
Radeonsi is going to use nir tess factor write, so need to
remap tess factor location.

RADV set tess factor driver location to be 0 and 1 in
get_linked_variable_location(). While radeonsi also set them
to be 0 and 1 in st->map_io aka. si_shader_io_get_unique_index_patch().

We could just set them to be 0 and 1 at the beginning of
ac_nir_lower_hs_outputs_to_mem(), but in order to keep the
location map at the same place, we still do this in
lower_hs_output_store().

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
c06329eb3f ac/nir: tcs write tess factor support pass by reg
For radeonsi usage.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
e070a9e8d0 ac/nir: move store_var_components to common place
It will be shared by other nir lowering too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Alyssa Rosenzweig
f2617944bf panfrost: Don't round up Midgard polygon list BOs
Rounding up the polygon list BO can waste large amounts of memory. In a common
case I observed, it rounded up 11MB to 16MB, wasting 5MB. That adds up quickly
across processes, especially on the 2GB machines.

This only applies to Midgard. On Bifrost and newer, the driver does not
explicitly allocate this data structure. Cc stable because this rounding is
incorrect and the increase in RAM usage can cause real problems (especially
given how slow the shrinker is).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21831>
2023-03-16 04:13:46 +00:00
Timothy Arceri
174d6e6a54 glsl: allow 64-bit integer on RHS of shift
Fixes: 9ba9a7f854 ("glsl: Add 64-bit integer support to some operations.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6862

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21919>
2023-03-16 02:26:30 +00:00
Daniel Schürmann
39c828cb9f aco: remove aco::rt_stack variable
Since we initialize scratch in the RT proglog,
there is no need for this variable anymore.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
f123d65e9f radv/rt: use prolog for raytracing shaders
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Friedrich Vock
bea022d1f6 radv/rt: Add shader config combination/postprocessing utils
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Friedrich Vock
0569b350ed radv: Emit RT shader VA user SGPR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
a16df842a6 radv: compile rt_prolog
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
4b92a53285 radv: add radv_create_rt_prolog()
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
6446b79168 aco: implement select_rt_prolog()
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
7d35bf24f6 aco: create hw_init_scratch() function for p_init_scratch lowering
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
2fee99a36c aco: implement load_ray_launch_{id|size}
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
c7c68e1193 aco: move rt_dynamic_callable_stack_base_amd to VGPR
In future, we will use a VGPR arg for that between RT stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
1f01a86b36 aco: don't set private_segment_buffer/scratch_offset on GFX9+
It is unused. Also don't initialize scratch in raytracing stages as it gets
initialized in the prolog shader.

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
a33b9d43d8 aco: add RT stage enums
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Daniel Schürmann
c38b8678c9 radv: add RT shader handling to radv_postprocess_config
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Daniel Schürmann
3f03eebf04 radv: add RT stages to radv_get_shader_name()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Daniel Schürmann
650f386bdd radv: handle RT stages in radv_nir_shader_info_pass()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Daniel Schürmann
d5de56bf59 radv: add RT shader args
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Daniel Schürmann
5ede3b1c6b mesa: add gl_shader_stage_is_rt()
to indicate raytracing shader stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Rob Clark
b78fc0ae48 driconf: Work around incorrect GI discard/invalidate
Genshin Impact does a depth+stencil invalidate (or discard, not sure
which entrypoint they are using) and then proceeds to do draws with
depth test enabled.  For IMRs (or freedreno in sysmem mode) this is no
problem.  But for tilers that use this as a hint that they can skip the
z/s tile load, it is.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>
2023-03-16 00:56:37 +00:00
Rob Clark
a66c62420e driconf: Add ignore_discard_framebuffer option
Some apps use glDiscardFramebuffer()/glInvalidateFramebuffer() when they
only kidding.  Add a knob to disable that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>
2023-03-16 00:56:37 +00:00
Rob Clark
976d964a35 mesa: Rework discard_framebuffer()
Decouple the logic turning API attachment enums into gl_buffer_index.
This will make it easier to re-use discard_attachments() internally (See
!21910)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>
2023-03-16 00:56:37 +00:00
Lynne
f5e5ec180c aco_validate: allow for wave32 in p_dual_src_export_gfx11
Fixes RADV_PERFTEST=pswave32

Fixes: bb90d29660 ("aco: add p_dual_src_export_gfx11 for dual source blending on GFX11")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21934>
2023-03-15 23:55:41 +00:00
Mark Janes
a2e5e7daa0 intel: use generated helpers for Wa_1409433168/Wa_16011107343
HSD 1306463417 is a hardware defect.  The originating software
workaround for the issue is Wa_1409433168.  Convert all references to
the software workaround number, and use generated helpers instead of
GFX comparisons.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21914>
2023-03-15 23:31:08 +00:00
Emma Anholt
4466098324 ci/turnip: Move some more of the 1.3.5 new xfails under links.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>
2023-03-15 23:07:21 +00:00
Emma Anholt
5e3d36199f ci/turnip: Disable dEQP-VK.image.queue_transfer.* for now.
We're waiting on the upstream CTS fix to land.  Until then, quiet the spam
in #freedreno-ci to see if we have any other flakes we need to be managing
right now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>
2023-03-15 23:07:21 +00:00
Emma Anholt
45dc05d455 ci/turnip: Clear out stale xfails.
These were all fixed in the CTS, but missed from removal due to fractional runs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>
2023-03-15 23:07:21 +00:00
Emma Anholt
78d4a82d30 turnip: Don't push inline uniform buffer contents outside constlen.
This would apparently lead to trying to load from this inline uniform
buffer in later submits.

Fixes: 37cde2c634 ("tu: Rewrite inline uniform implementation")
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8219
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21915>
2023-03-15 23:07:21 +00:00