aco: add RT stage enums

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
This commit is contained in:
Daniel Schürmann 2022-05-13 12:06:49 +02:00 committed by Marge Bot
parent c38b8678c9
commit a33b9d43d8
3 changed files with 28 additions and 9 deletions

View file

@ -306,7 +306,13 @@ setup_variables(isel_context* ctx, nir_shader* nir)
break;
}
case MESA_SHADER_COMPUTE:
case MESA_SHADER_TASK: {
case MESA_SHADER_TASK:
case MESA_SHADER_RAYGEN:
case MESA_SHADER_CLOSEST_HIT:
case MESA_SHADER_MISS:
case MESA_SHADER_CALLABLE:
case MESA_SHADER_INTERSECTION:
case MESA_SHADER_ANY_HIT: {
ctx->program->config->lds_size =
DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule);
break;
@ -774,6 +780,12 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c
case MESA_SHADER_COMPUTE: sw_stage = sw_stage | SWStage::CS; break;
case MESA_SHADER_TASK: sw_stage = sw_stage | SWStage::TS; break;
case MESA_SHADER_MESH: sw_stage = sw_stage | SWStage::MS; break;
case MESA_SHADER_RAYGEN:
case MESA_SHADER_CLOSEST_HIT:
case MESA_SHADER_MISS:
case MESA_SHADER_CALLABLE:
case MESA_SHADER_INTERSECTION:
case MESA_SHADER_ANY_HIT: sw_stage = SWStage::RT; break;
default: unreachable("Shader stage not implemented");
}
}
@ -822,6 +834,8 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c
hw_stage = HWStage::GS; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
else if (sw_stage == SWStage::TES_GS && ngg)
hw_stage = HWStage::NGG; /* GFX10+: TES+GS merged into an NGG GS */
else if (sw_stage == SWStage::RT)
hw_stage = HWStage::CS; /* Raytracing shaders run as CS */
else
unreachable("Shader stage not implemented");

View file

@ -1945,14 +1945,15 @@ struct Block {
*/
enum class SWStage : uint16_t {
None = 0,
VS = 1 << 0, /* Vertex Shader */
GS = 1 << 1, /* Geometry Shader */
TCS = 1 << 2, /* Tessellation Control aka Hull Shader */
TES = 1 << 3, /* Tessellation Evaluation aka Domain Shader */
FS = 1 << 4, /* Fragment aka Pixel Shader */
CS = 1 << 5, /* Compute Shader */
TS = 1 << 6, /* Task Shader */
MS = 1 << 7, /* Mesh Shader */
VS = 1 << 0, /* Vertex Shader */
GS = 1 << 1, /* Geometry Shader */
TCS = 1 << 2, /* Tessellation Control aka Hull Shader */
TES = 1 << 3, /* Tessellation Evaluation aka Domain Shader */
FS = 1 << 4, /* Fragment aka Pixel Shader */
CS = 1 << 5, /* Compute Shader */
TS = 1 << 6, /* Task Shader */
MS = 1 << 7, /* Mesh Shader */
RT = 1 << 8, /* Raytracing Shader */
/* Stage combinations merged to run on a single HWStage */
VS_GS = VS | GS,
@ -2036,6 +2037,8 @@ static constexpr Stage tess_control_hs(HWStage::HS, SWStage::TCS);
static constexpr Stage tess_eval_es(HWStage::ES,
SWStage::TES); /* tesselation evaluation before geometry */
static constexpr Stage geometry_gs(HWStage::GS, SWStage::GS);
/* Raytracing */
static constexpr Stage raytracing_cs(HWStage::CS, SWStage::RT);
struct DeviceInfo {
uint16_t lds_encoding_granule;

View file

@ -868,6 +868,8 @@ print_stage(Stage stage, FILE* output)
fprintf(output, "mesh_ngg");
else if (stage == task_cs)
fprintf(output, "task_cs");
else if (stage == raytracing_cs)
fprintf(output, "raytracing_cs");
else
fprintf(output, "unknown");