In theory, this will let us track the depth and render caches
separately. Right now, they're just wrappers around
brw_render_cache_set_*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 4a09070295)
This makes sure we flush things out of other caches prior to using a
surface through the render cache. Currently, this is a no-op because GL
won't let you bind anything other than a color surface as color so it
should never end up in the depth cache. However, this does complete the
flush/add_bo pair for regular drawing which will be required for the
next commit.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 622786c20c)
Without this initialization the temp registers used in tgsi_declaration
may used random indices, and this may result in failing translation from TGSI
with an error message "GPR limit exceeded", because the random index is greater
then the allowed limit implying that the shader uses more temporary registers then
available.
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5d6470d26b)
Respect the std430 rules for determining offset and size of struct
members when using a std430 buffer. std140 rules lead to wrong buffer
offsets in that case.
Fixes my test case attached in Bugzilla. No piglit changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104492
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 7e025def6d)
If alpha-to-coverage is enabled, we have to compute alpha
even if color writes are disabled.
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit f222cf3c6d)
Upon reception of an event that lowered the number of active back buffers,
the code would immediately try to free all back buffers with an id equal to or
higher than the new number of active back buffers.
However, that could lead to an active or to-be-active back buffer being freed,
since the old number of back buffers was used when obtaining an idle back
buffer for use.
This lead to crashes when lowering the number of active back buffers by
transitioning from page-flipping to non-page-flipping presents.
Fix this by computing the number of active back buffers only when trying to
obtain a new back buffer.
Fixes: 15e208c4cc ("loader/dri3: Don't accidently free buffer holding new back content")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Andriy.Khulap <andriy.khulap@globallogic.com>
Tested-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
(cherry picked from commit 897c54d522)
anv_extensions usage from anv_icd was bringing the unwanted dependency
of mako templates for the latter. We don't want that since it will
force the dependency even for distributable tarballs which was not
needed until now.
Jason suggested this approach.
v2: Patch simplification (Jason).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104551
Fixes: 0ab04ba979 ("anv: Use python to generate ICD json files")
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit a1901d092c)
If they were promoted from inputs/outputs, they could have a
non-zero value left over, which messed with our store handling.
Fixes: 06f05040eb "radv: Link shaders."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 67e09c8b45)
These are just shaders reads, so we need to invalidate L1.
Fixes: 6dbb0eaccc "radv: handle subpass cache flushes"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit f2c9f13ec2)
When rasterization is disabled we can have that few.
Fixes: 76603aa90b "radv: Drop the default viewport when 0 viewports are given."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 1c78e4f053)
Seems like users are actually hitting 0xFFFFFFFF actually making
things broken for them, and the mad max regression is fixed, so
lets put this in once more.
v2: Use 0xf for depth-only htile. (Dave)
Fixes: af2844116f "radv: Revert HTILE reset word to 0xFFFFFFFF."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5158603182)
This reverts commit 5951578043.
The mentioned commit causes a hang in DoW3 on Vega.
Fixes: 5951578043 "radv/gfx9: fix block compression texture views."
Acked-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 516a80b579)
This should fix:
dEQP-VK.pipeline.sampler.view_type.*.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
and a few others in that area.
Fixes: b11c4a5546 (radv: add texture descriptor/fmask/cmask support for GFX9)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a4c23ce1b6)
amdvlk is probably more subtle than this but it never uses
the inv cb/db variants, we fail some CTS tests without this.
Fixes:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
Fixes: c2fbeb7ca0 (radv: add GFX9 cache flushing support.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (for now :-)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 868377ab33)
This ports a fix from amdvlk, to fix the sizing for mip levels
when block compressed images are viewed using uncompressed views.
Fixes:
dEQP-VK.image.texel_view_compatible.graphic.extended*bc*
Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5951578043)
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 420627e6e7)
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 09612a62e1)
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit d08f267814)
It's legal to a pipeline stat query on a compute queue,
but we'd emit the wrong packet here. This should fix it to emit
the correct packet.
Noticed while inspecting the mpv hang.
Fixes: ad61eac250 (radv: factor out eop event writing code. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ec1edd0fd2)
The event emission wasn't sending the correct packet for gfx8 compute
queues, which explains why it works on vega fine.
This fixes the mpv vulkan hang.
Fixes: ad61eac250 (radv: factor out eop event writing code. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 38e4467e99)
HW resolve does not support it either.
Fixes: 2a04f5481d "radv/meta: select resolve paths"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a636208ace)
Framebuffer is from 0,0, not (dst.x, dst.y).
Fixes: 69136f4e63 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit da192b50b2)
The position start at (dst.x, dst.y), so if we want the source to
start at (src.x, src.y), we have to offset by (src.x-dst.x,src.y-dst.y).
Haven't tested that this fixed anything yet, but found by inspection.
Fixes: 69136f4e63 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 73279da41d)
the samples_identical instruction returns 0 if they are differet, so
we have to do the extra work if the result is 0, not if it is != 0.
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit c39947ce30)
fixes: The commit addresses earlier commits 40a01c9a0e and 8d745abc00
which did not land in branch.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
From Vulkan spec:
"descriptorCount is the number of descriptors contained in the binding,
accessed in a shader as an array. If descriptorCount is zero this
binding entry is reserved and the resource must not be accessed from
any stage via this binding within any pipeline using the set layout."
Fixes:
dEQP-VK.binding_model.descriptor_update.empty_descriptor.uniform_buffer
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit e63adf8b1e)
After executing a secondary command buffer, we need to update certain
state on the primary command buffer to reflect changes by the secondary.
Otherwise subsequent commands may not have the correct state set.
This fixes various issues (rendering errors, GPU hangs) seen after
executing secondary command buffers in some cases.
v2 (Jason Ekstrand):
- Reset to invalid values instead of pulling from the secondary
- Change the comment to be more descriptive
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 4fd85617c1)
intel_batchbuffer_emit_float is dead code, it should go.
intel_batchbuffer_emit_dword only had one user, which had bungled using
them by forgetting to call intel_batchbuffer_require_space first. So it
seems wise to delete these unsafe helpers.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit be144e251c)
intel_batchbuffer_emit_dword doesn't reserve space for the DWord it
emits. In the past, we had some reserved batch space to ensure this
worked. With the switch to growing batches, we need to actually request
space so that we grow if necessary.
Fixes: 2c46a67b41 (i965: Delete BATCH_RESERVED handling.)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 1c9f1a28c0)
If we have a color attachment, but its writes are masked, this would
have still returned true. This is inconsistent with how HasWriteableRT
in 3DSTATE_PS_BLEND is set, which does take the mask into account.
This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA
if the fragment shader does use UAVs, meaning the fragment shader may
not be invoked because HasWriteableRT is false. Specifically, this was
seen to occur when the shader also enables early fragment tests: the
fragment shader was not invoked despite passing depth/stencil.
Fix by taking the color write mask into account in this function. This
is consistent with how things are done on i965.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 12f4e00b69)
Should be 0x80000000 instead of 0x8000000.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit 396c006d90)
Fixes hangs seen due to the lock not being released here.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 00a81e9909)
The in-place resolve probably has some additional restrictions when not
operating on a super tiled surface. Disable it on non-supertiled surfaces
for now to work around a GPU hang.
Fixes: 78ade65956 ("etnaviv: Do GC3000 resolve-in-place when possible")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit 0158565924)
Commit 2f421651ac ("egl: let each platform decided how to handle
LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
function parameter.:
src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared identifier 'disp'
Rather than just fixing 'disp', rename the function parameter 'dpy' to
'disp' to align with the other EGL platforms' implementations.
Fixes: 2f421651ac ("egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Rob Herring <robh@kernel.org>
(cherry picked from commit aa187fe7bf)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/egl/drivers/dri2/platform_android.c
My refactor in 47273d7312 missed this early return; because
of it, setting UseFallback one layer above actually prevented the
software path from being used.
Remove this early return and let each platform's dri2_initialize_*()
decide what it can do with the LIBGL_ALWAYS_SOFTWARE restriction.
platform_{surfaceless,x11,wayland} were already handling it themselves.
Fixes: 47273d7312 "egl: set UseFallback if LIBGL_ALWAYS_SOFTWARE is set"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Brendan King <Brendan.King@imgtec.com>
(cherry picked from commit 2f421651ac)
Note: the following happens only when using slibtool.
Since this is a very serious breakage, we will keep the workaround until
a better solution is available.
DRI modules store the address of the dispatch table in a TLS variable,
_glapi_tls_Dispatch.
Changes to the way libEGL is built in d884d8d007 resulted in
it being statically linked against libglapi, and thus containing its own
copy of _glapi_tls_Dispatch. The result was that some applications would
fail to work (e.g. deqp-egl, which dynamically loads libEGL), due to the
DRI module storing the dispatch table address in one copy of
_glapi_tls_Dispatch, and libEGL obtaining the address from another copy
of the variable.
Fixes: d884d8d007 "egl/dri: link directly to libglapi.so"
Signed-off-by: Brendan King <Brendan.King@imgtec.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit e491bffc5c)
For copies the texture unit needs to know the depth format so
it can read the htile data properly.
This fixes:
dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.load.clear
Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit d2acf97e49)
