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radv/gfx9: use a bigger hammer to flush cb/db caches.

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amdvlk is probably more subtle than this but it never uses
the inv cb/db variants, we fail some CTS tests without this.

Fixes:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.

Fixes: c2fbeb7ca0 (radv: add GFX9 cache flushing support.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (for now :-)
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-12-29 11:00:34 +10:00
parent 5951578043
commit 868377ab33
1 changed files with 8 additions and 1 deletions
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9
src/amd/vulkan/si_cmd_buffer.c
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@ -991,6 +991,11 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
if (chip_class >= GFX9 && flush_cb_db) {
unsigned cb_db_event, tc_flags;
#if 0
/* This breaks a bunch of:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
use the big hammer always.
*/
/* Set the CB/DB flush event. */
switch (flush_cb_db) {
case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
@ -1003,7 +1008,9 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
/* both CB & DB */
cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
}
#else
cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
#endif
/* TC | TC_WB = invalidate L2 data
* TC_MD | TC_WB = invalidate L2 metadata
* TC | TC_WB | TC_MD = invalidate L2 data & metadata