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i965: Add more precise cache tracking helpers

Browse source 
In theory, this will let us track the depth and render caches
separately.  Right now, they're just wrappers around
brw_render_cache_set_*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 4a09070295)
This commit is contained in:
Jason Ekstrand 2017-11-03 16:01:28 -07:00 • committed by Emil Velikov
parent e66bafa973
commit 6f5752dba7
6 changed files with 49 additions and 13 deletions
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12
src/mesa/drivers/dri/i965/brw_draw.c
View file

@ -426,7 +426,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
min_layer, num_layers,
disable_aux);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
brw_cache_flush_for_read(brw, tex_obj->mt->bo);
if (tex_obj->base.StencilSampling ||
tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
@ -450,7 +450,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
intel_miptree_prepare_image(brw, tex_obj->mt);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
brw_cache_flush_for_read(brw, tex_obj->mt->bo);
}
}
}
@ -563,11 +563,11 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
depth_written);
}
if (depth_written)
brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
brw_depth_cache_add_bo(brw, depth_irb->mt->bo);
}
if (stencil_irb && brw->stencil_write_enabled)
brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
brw_depth_cache_add_bo(brw, stencil_irb->mt->bo);
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
struct intel_renderbuffer *irb =
@ -580,7 +580,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
_mesa_get_render_format(ctx, intel_rb_format(irb));
enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
brw_render_cache_set_add_bo(brw, irb->mt->bo);
brw_render_cache_add_bo(brw, irb->mt->bo);
intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
isl_format,
@ -595,7 +595,7 @@ intel_renderbuffer_move_temp_back(struct brw_context *brw,
if (irb->align_wa_mt == NULL)
return;
brw_render_cache_set_check_flush(brw, irb->align_wa_mt->bo);
brw_cache_flush_for_read(brw, irb->align_wa_mt->bo);
intel_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
irb->mt,

4
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -333,9 +333,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
}
if (depth_mt)
brw_render_cache_set_check_flush(brw, depth_mt->bo);
brw_cache_flush_for_depth(brw, depth_mt->bo);
if (stencil_mt)
brw_render_cache_set_check_flush(brw, stencil_mt->bo);
brw_cache_flush_for_depth(brw, stencil_mt->bo);
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,

9
src/mesa/drivers/dri/i965/genX_blorp_exec.c
View file

@ -225,7 +225,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
* data.
*/
if (params->src.enabled)
brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
brw_cache_flush_for_read(brw, params->src.addr.buffer);
brw_cache_flush_for_render(brw, params->dst.addr.buffer);
brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
@ -293,9 +294,9 @@ retry:
brw->ib.index_size = -1;
if (params->dst.enabled)
brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
brw_render_cache_add_bo(brw, params->dst.addr.buffer);
if (params->depth.enabled)
brw_render_cache_set_add_bo(brw, params->depth.addr.buffer);
brw_depth_cache_add_bo(brw, params->depth.addr.buffer);
if (params->stencil.enabled)
brw_render_cache_set_add_bo(brw, params->stencil.addr.buffer);
brw_depth_cache_add_bo(brw, params->stencil.addr.buffer);
}

29
src/mesa/drivers/dri/i965/intel_fbo.c
View file

@ -1021,6 +1021,35 @@ brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo)
brw_render_cache_set_clear(brw);
}
void
brw_cache_flush_for_read(struct brw_context *brw, struct brw_bo *bo)
{
brw_render_cache_set_check_flush(brw, bo);
}
void
brw_cache_flush_for_render(struct brw_context *brw, struct brw_bo *bo)
{
}
void
brw_render_cache_add_bo(struct brw_context *brw, struct brw_bo *bo)
{
brw_render_cache_set_add_bo(brw, bo);
}
void
brw_cache_flush_for_depth(struct brw_context *brw, struct brw_bo *bo)
{
brw_render_cache_set_check_flush(brw, bo);
}
void
brw_depth_cache_add_bo(struct brw_context *brw, struct brw_bo *bo)
{
brw_render_cache_set_add_bo(brw, bo);
}
/**
* Do one-time context initializations related to GL_EXT_framebuffer_object.
* Hook in device driver functions.

6
src/mesa/drivers/dri/i965/intel_fbo.h
View file

@ -233,6 +233,12 @@ void brw_render_cache_set_clear(struct brw_context *brw);
void brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo);
void brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo);
void brw_cache_flush_for_read(struct brw_context *brw, struct brw_bo *bo);
void brw_cache_flush_for_render(struct brw_context *brw, struct brw_bo *bo);
void brw_cache_flush_for_depth(struct brw_context *brw, struct brw_bo *bo);
void brw_render_cache_add_bo(struct brw_context *brw, struct brw_bo *bo);
void brw_depth_cache_add_bo(struct brw_context *brw, struct brw_bo *bo);
unsigned
intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples);

2
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -3007,7 +3007,7 @@ intel_update_r8stencil(struct brw_context *brw,
}
}
brw_render_cache_set_check_flush(brw, dst->bo);
brw_cache_flush_for_read(brw, dst->bo);
src->r8stencil_needs_update = false;
}