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Author SHA1 Message Date
Emma Anholt
6db1f93699 glsl: Delete the optimize_redundant_jumps pass. 
Nothing here that NIR doesn't do.  No effect on shader-db of hsw or
softpipe.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
 2021-12-20 14:47:57 -08:00
Emma Anholt
c2ead6c9b5 glsl: Delete the vectorization opt pass. 
Nothing uses it, and i965 was the last thing to.  Even if I enable it for
softpipe or crocus, it quickly causes NIR validation failures in shader-db
from swizzles outside the bounds of vectors.  Retire it in favor of
nir_opt_vectorize().

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
 2021-12-20 14:47:57 -08:00
Rob Clark
8a21b2fda0 freedreno/ir3: Dump const state with shader disasm 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
 2021-12-20 19:47:35 +00:00
Rob Clark
9766a5721d freedreno/computerator: Mark shader bo for dumping 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
 2021-12-20 19:47:35 +00:00
Rob Clark
d1edc6d9a1 freedreno/computerator: Fix @buf header 
Order is important in the grammar, the more specific match needs to go
first.

Fixes: ba1c989348 ("freedreno/computerator: pass iova of buffer to const register")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
 2021-12-20 19:47:35 +00:00
Rob Clark
78c53f4888 freedreno/ir3: Handle instr->address when cloning 
Without this, a cloned instruction that takes full regs will trigger an
ir3_validate assert.  This can happen, for ex, if an instruction that
writes p0.x and has a relative src gets cloned in ir3_sched.

Fixes an assert in Genshin Impact with a debug build.

Fixes: 9af795d9b9 ("ir3: Make ir3_instruction::address a normal register")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
 2021-12-20 19:47:35 +00:00
Alyssa Rosenzweig
1d21de788d pan/bi: Specialize shaders for IDVS 
We need to compile multiple variants and report them together in a
common shader info. To do so, we split off per-variant shader infos and
combine at the end.

glmark2 is very happy: https://people.collabora.com/~alyssa/idvs-g52.txt
Highlights include -bshading up 41% fps and -bbump:bump-render=high-poly
up 62% faster

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
c59977c3bf pan/bi: Add helper to decide if IDVS should be used 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
a211d2b4e4 pan/bi: Use position shader ST_CVT path 
We need to use a preload instead of the LEA_ATTR. Not sure why.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
fe8ec31114 pan/bi: Split out varying store paths 
This means we don't need to special case IDVS quite so hard.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
e0771d5832 pan/bi: Remove the "wrong" stores in IDVS variants 
Position shaders should only write gl_Position (and gl_PointSize on
Valhall), varying shaders should only write varyings.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
fba5936fdb pan/bi: Add IDVS mode to bi_context 
Various parts of the compiler switch behaviour based on IDVS variant.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
c7fae2c896 pan/bi: Allow UBO pushing to run multiple times 
For IDVS.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
e2f7871bcf pan/bi: Extract bi_finalize_nir 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
62d46c7ee6 panfrost: Add panfrost_compile_inputs->no_idvs option 
panvk will want IDVS support eventually, but not right now. Allow the
driver to opt out of IDVS in the mean time.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
2ff3c4a636 panfrost: Align instance size for IDVS 
Hardware requirement. Failing to do this raises a DATA_INVALID_FAULT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
79356b2e5f panfrost: Skip rasterizer discard draws without side effects 
Minor optimization, but more importantly fixes an interaction of IDVS
with rasterizer discard.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
f5412409db panfrost: Extract panfrost_batch_skip_rasterization 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
3a49f4798c panfrost: Emit IDVS jobs 
When trying to draw with an IDVS capable shader.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
e5b0c514d8 panfrost: Extract panfrost_draw_emit_vertex_section 
To be shared with IDVS.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
4d8d987f1a panfrost: Set secondary_* fields for IDVS 
Easy now that we've split everything out nicely.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
29f63c6283 panfrost: Remove regalloc from v6.xml 
These fields were not introduced until v7, fix that.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
83356c58f8 panfrost: Split out regalloc/preload helpers 
The logic gets duplicated if IDVS is in use.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
9e65ebb67a panfrost: Add IDVS fields to shader_info 
This lets the compiler decide if IDVS should be used.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
dc4fe86a01 panfrost: Treat IDVS jobs as tiler for scoreboarding 
These need to be chained and need to provoke a fragment job when we're
done.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:41 +00:00
Alyssa Rosenzweig
8dc1936faa panfrost: Fix Secondary Shader field 
Off-by-one on the start.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Fixes: 73e80994d5 ("panfrost: Add secondary shader XML fields")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
b27bbbe0c9 panfrost: Remove unused shader info bits 
These were only used to infer preloading and can be deleted.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
7358edad42 panfrost: Set preload descriptor more accurately 
Preload exactly what the shader needs, based on the compiler's mask of
uninitialized registers, rather than trying to sync pan_shader.h with
the behaviour of code gen. Would've saved me some debugging over the
years...

As a bonus this avoids preloading unnecessary registers, particularly in
compute shaders. In theory this should reduce power consumption.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
52fe998aa6 panfrost: Track preloaded registers 
We already collect this information. We may as well make use of it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
e8566f7529 pan/indirect_draw: Support IDVS jobs 
Handle as tiler jobs with an extra vertex DCD at the end.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
37ab248c77 pan/indirect_draw: Split out update_dcd 
This is common between vertex/tiler jobs and needs to be duplicated for
IDVS jobs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
d696183d4d pan/indirect_draw: Don't upload garbage UBO 
There should never be a CPU pointer in GPU memory, let's say that...

Fixes: 2e6d94c198 ("panfrost: Add helpers to support indirect draws")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Rafael Antognolli
e9b509755b intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP 
On XeHP+, Binding Table Pointers are an offset relative to the Surface
State Base Address anymore. Instead, they are relative to the State
Binding Table Pool Address, which is set by the command above.

We emit that command (pointing to the same address as the Surface
State Base Addresss), and everything should stay working as before.

Reworks:
 * Jordan: Add iris
 * Jordan: Drop i965
 * Ken: Set MOCS to avoid a major perf impact. (Found by Felix DeGrood.)
 * Jordan: Shrink size from 2MiB to actual iris, anv usage
 * Lionel: Add BINDING_TABLE_POOL_BLOCK_SIZE

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4995
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
[jordan.l.justen@intel.com: Add Iris, adjust sizes]

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
 2021-12-20 17:58:13 +00:00
Jordan Justen
e6fc231184 anv: Add BINDING_TABLE_POOL_BLOCK_SIZE 
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
 2021-12-20 17:58:13 +00:00
Jordan Justen
1ed7a65e6d intel/genxml/12.5: Remove bt-pool enable from 3DSTATE_BINDING_TABLE_POOL_ALLOC 
This was dropped in gfx12.5.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
 2021-12-20 17:58:13 +00:00
Alyssa Rosenzweig
9da1787488 docs/macos: Update for recent Mesa changes 
- Default c_std is now c11, no need to workaround
  89b4f337d5 ("c_std=c11 in meson default_options")

- gallium-xlib has been renamed to xlib:
  76791db088 ("mesa/x11: Remove the swrast-classic-based fake libGL")

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14216>
 2021-12-20 17:53:27 +00:00
Jason Ekstrand
88b9b68f30 vulkan/runtime: Validate instance version on 1.0 implementations 
This isn't something that ANV or RADV have cared about in a long time
but, as people bring up new Vulkan drivers, shipping Vulkan 1.0 is still
a thing that happens in Mesa.  The common code should also implement the
1.0 rules.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14150>
 2021-12-20 16:45:55 +00:00
Jesse Natalie
64991d44a8 microsoft/compiler: Load synthesized sysvals via lowered io 
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
 2021-12-20 08:20:59 -08:00
Jesse Natalie
8d5b7450a4 microsoft/compiler: Delete non-sysval deref load/store code 
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
 2021-12-20 08:20:55 -08:00
Jesse Natalie
f30768f1d6 microsoft/compiler: Lower io 
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
 2021-12-20 08:20:52 -08:00
Jesse Natalie
f4d247c2e3 microsoft/compiler: Support lowered io (nir_intrinsic_load_input/store_output) 
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
 2021-12-20 08:20:11 -08:00
Simon Ser
0a9886cc45 renderonly: write down usage rules 
The renderonly helpers are extremely easy to mis-use. Write down
the expectations.

I've seen *many* mistakes in the past, including:

- Forgetting to create the scanout resource on import [1] [2], causing
  bugs such as [3].
- Assuming the scanout resource always exists [4].
- Returning a GEM handle valid for the driver's internal DRM FD, but
  invalid for the caller's DRM FD [5].
- Not implementing resource_get_param, breaking stride/offset/modifier
  queries when no scanout resource is available [6] [7].

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>

[1]: 4aac98f8a6
[2]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12018
[3]: https://github.com/swaywm/wlroots/issues/2795
[4]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12081
[5]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074
[6]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12362
[7]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12418>
 2021-12-20 12:42:03 +01:00
Dave Airlie
d4af7d2519 mesa/st: move st strings handling into mesa 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
 2021-12-20 04:35:41 +00:00
Dave Airlie
8956b7f38f mesa/st: migrate barrier code into mesa 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
 2021-12-20 04:35:41 +00:00
Dave Airlie
294dc8fa04 mesa/st: move msaa functionality into multisample.c 
This moves some state track code into main

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
 2021-12-20 04:35:41 +00:00
Dave Airlie
f5eda36760 mesa/st: move get sample position code to static in mesa 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
 2021-12-20 04:35:41 +00:00
Dave Airlie
b6fd811d2c mesa/compute: refactor compute launch to look more like draw 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
 2021-12-20 13:41:02 +10:00
Dave Airlie
56f5e69497 mesa/st: migrate compute dispatch to mesa 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
 2021-12-20 13:40:57 +10:00
Dave Airlie
20de14c57e mesa/st: refactor compute dispatch to fill grid info earlier. 
This fills the grid info earlier and uses info in validation

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
 2021-12-20 13:40:42 +10:00
Kostiantyn Lazukin
e9cc1633a2 util/ra: Fix numeric overflow during bitset allocation 
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Kostiantyn Lazukin <kostiantyn.lazukin@globallogic.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5752
Fixes: d4a4cd20d5 ("util/ra: use adjacency matrix for undirected graph")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14224>
 2021-12-19 13:10:26 -08:00