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Author SHA1 Message Date
Brian
5ef3a2c06d document GLSL float f/F suffix bug 2007-11-27 10:31:55 -07:00
Brian
4fe3bf2d77 set fp->UsesKill when emitting OPCODE_KIL 2007-11-27 10:31:55 -07:00
Brian
92e4090b4c add a few more logicop modes, simplify code 2007-11-27 10:31:55 -07:00
Brian
74cd0b459f improve 24-bit Z to 32-bit Z conversion 2007-11-27 10:31:55 -07:00
Xiang, Haihao
46e03d584a i965: The jump instruction count is added 
to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
 2007-11-27 09:45:32 +08:00
Keith Whitwell
a8fee3a498 i915: Catch cases where not all state is emitted for a new batchbuffer. 
This could lead to incorrect rendering or even lockups.
 2007-11-26 17:49:29 +01:00
Michel Dänzer
63e6bfe8db i915: Some additional blit fixes and assertions. 2007-11-26 17:35:35 +01:00
Michel Dänzer
42108629e8 libGL: Make sure a valid value is returned for GLX_BIND_TO_MIPMAP_TEXTURE_EXT. 
If the server didn't send a value, assume it's not supported.

A more generic solution might be better for this kind of problem, but an
attempt for this failed (see https://bugs.freedesktop.org/show_bug.cgi?id=9264)
and this allows compiz to work with drivers that support
GL_EXT_framebuffer_object.
 2007-11-25 14:20:36 +01:00
Michel Dänzer
7dd5ced962 intel: Fix relative symlinks. 2007-11-25 14:17:02 +01:00
Brian
be1fa5b3d7 better test of point attenuation 2007-11-23 16:19:25 -07:00
Brian
88b067cb04 #define GL_GLEXT_PROTOTYPES to silence warning 2007-11-23 14:35:46 -07:00
Brian
999b55663a Consolidate texture fetch code and use partial derivatives when possible. 2007-11-23 12:01:57 -07:00
Brian
ba16243884 Fix parsing of gl_FrontLightModelProduct.sceneColor, don't segfault on variable array indexes. 2007-11-23 10:25:48 -07:00
Brian
c14d969a69 need to check border width in sample_linear_2d() - fixes failed assertion in texwrap.c test 2007-11-23 09:14:39 -07:00
Brian
0fd679a190 Consolidate point size computation, clamping in get_size(). 
Also, apply user-defined clamp limits to point size even when not using
attentuation or program-computed size.
 2007-11-22 09:34:38 -07:00
Brian
ccb1c9df00 Print point/line size range limits 2007-11-22 09:34:38 -07:00
Roland Scheidegger
3d51c79001 fix z buffer read/write issue with rv100-like chips and old ddx 2007-11-22 02:49:15 +01:00
Eric Anholt
93c98a4669 [965] Replace 965 texture format code with common code. 
The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
 2007-11-20 11:30:12 -08:00
Eric Anholt
e962997429 [965] Remove dead exec vfmt code which was replaced by generic vbo code. 2007-11-20 11:30:10 -08:00
Brian
827e72de75 clamp lambda to Min/MaxLod 2007-11-20 08:24:46 -07:00
Eric Anholt
3821d15e06 [965] Add INTEL_DEBUG=fall debugging output. 2007-11-19 15:29:31 -08:00
Eric Anholt
27674c4135 [965] Convert DBG macro to use FILE_DEBUG_FLAG like i915. 2007-11-19 15:28:26 -08:00
Brian
87373e3072 fix some texture format assertions, etc 2007-11-19 10:37:54 -07:00
Brian
22a374fc3f fix out-of-bounds array index (ix=-1) 2007-11-19 09:55:47 -07:00
Eric Anholt
f00a64999c [intel] Add 965 support to shared intel_blit.c 
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
 2007-11-16 17:29:30 -08:00
Eric Anholt
9b461d4d02 [i915] Pass static region names in so debugging says more than "static region". 2007-11-16 16:18:30 -08:00
Eric Anholt
5ef6803b7a [intel] Move additional code to be shared from intel_context.h to intel/. 2007-11-16 16:05:11 -08:00
Eric Anholt
5cdf3972de [intel] Move intel_tex.h into place, forgotten in the previous commit. 2007-11-16 15:51:34 -08:00
Eric Anholt
8775bf475b [965] Add batchbuffer decode for several more packets. 2007-11-16 15:44:11 -08:00
Eric Anholt
a66413874d [intel] Fix typos in intel_chipset.h macros. 2007-11-16 15:36:18 -08:00
Eric Anholt
3bd07ba0d4 [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them. 2007-11-16 15:36:18 -08:00
Eric Anholt
f7e0513d70 [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat. 2007-11-16 15:36:18 -08:00
Eric Anholt
152aa6350d [intel] Add some doxygen notes on what the bufmgr_fake block members mean. 2007-11-16 15:36:18 -08:00
Eric Anholt
c29e9e534e [intel] Add a simple relocation cache to the fake buffer manager. 
This is required for 965 performance, as it avoids a lot of repeated data
uploads of the state caches due to surface offsets in them.
 2007-11-16 15:36:18 -08:00
Eric Anholt
4bc625e378 [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c. 
They shouldn't be created, and this often helps catch stupid issues.
 2007-11-16 15:36:18 -08:00
Eric Anholt
00eb5635c6 [intel] Add support for multiple levels of relocation in bufmgr_fake. 
This is required for 965 support, which has relocations in other places than
just the batchbuffer.
 2007-11-16 15:36:18 -08:00
Eric Anholt
df3c530bed [i915] Push locking in intelClearWithTris down inside meta_draw_poly. 
The lock coverage and checks for cliprects were unneeded since the batchbuffer
will have INTEL_BATCH_CLIPRECTS anyway.  It appeared to be a leftover from
intelClearWithBlit.

This makes the locking requirements of i915 meta_draw_quad match i965
meta_draw_quad.
 2007-11-16 15:36:18 -08:00
Brian
8211b20026 added z/s keys to reset/step rotation 2007-11-16 15:19:05 -07:00
Brian
fb69fe58a0 Only emit texcoords for enabled units. Enable/disable units with 0..7 keys. 
Also, asst. clean-ups.
 2007-11-16 15:19:05 -07:00
Roland Scheidegger
96ba38a450 fix bogus assumption if ddx has set up surface reg for z buffer 
this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
 2007-11-15 01:13:16 +01:00
Roland Scheidegger
dab7c810e9 fix position invariant vertex programs for sw-tnl 
do the same math as for fixed function pipe, including
user clip planes.
(mostly resurrected from the dead t_vb_arbprogram.c code)
 2007-11-15 00:52:38 +01:00
Brian
f6ab1347d6 remove dependency on libGLU 2007-11-12 08:02:09 -07:00
Brian
b87ce5be82 add glw.pc.in to tarball list, remove from DEPEND_FILES 2007-11-12 07:51:55 -07:00
Xiang, Haihao
9bf5da906f i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730 2007-11-12 10:20:26 +08:00
Brian
578641941f test that point/line/quad rendering hits the right pixels 2007-11-09 17:02:51 -07:00
Eric Anholt
9724dc1ac7 [i915] Remove old frontbuffer rotation hack. 
This was replaced in previous releases of xserver/dri/libGL by reporting the
damage to the frontbuffer so that the server and driver could handle it
appropriately.
 2007-11-09 15:05:56 -08:00
Eric Anholt
7d4b89a2b3 [intel] By default, output batchbuffer decode to stderr like other debug info. 2007-11-09 14:27:33 -08:00
Eric Anholt
38c616260a [intel] Initialize a depth buffer if the visual has depth 24 but no stencil. 2007-11-09 14:27:33 -08:00
Eric Anholt
77a5bcaff4 [intel] Move over files that will be shared with 965-fbo work. 2007-11-09 14:27:33 -08:00
Brian
8b36166d29 check for texture and renderbuffer in check_end_texture_render() 2007-11-09 08:56:05 -07:00