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fix z buffer read/write issue with rv100-like chips and old ddx

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This commit is contained in:
Roland Scheidegger 2007-11-22 02:49:11 +01:00
parent 93c98a4669
commit 3d51c79001
1 changed files with 5 additions and 1 deletions
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6
src/mesa/drivers/dri/radeon/radeon_screen.c
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@ -720,7 +720,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->depthPitch = dri_priv->depthPitch;
/* Check if ddx has set up a surface reg to cover depth buffer */
screen->depthHasSurface = (sPriv->ddx_version.major > 4);
screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
/* these chips don't use tiled z without hyperz. So always pretend
we have set up a surface which will cause linear reads/writes */
((screen->chip_family & RADEON_CLASS_R100) &&
!(screen->chip_flags & RADEON_CHIPSET_TCL));
if ( dri_priv->textureSize == 0 ) {
screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;