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fix bogus assumption if ddx has set up surface reg for z buffer

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this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
This commit is contained in:
Roland Scheidegger 2007-11-15 01:13:16 +01:00
parent dab7c810e9
commit 96ba38a450
1 changed files with 1 additions and 2 deletions
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3
src/mesa/drivers/dri/radeon/radeon_screen.c
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@ -720,8 +720,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->depthPitch = dri_priv->depthPitch;
/* Check if ddx has set up a surface reg to cover depth buffer */
screen->depthHasSurface = ((sPriv->ddx_version.major > 4) &&
(screen->chip_flags & RADEON_CHIPSET_TCL));
screen->depthHasSurface = (sPriv->ddx_version.major > 4);
if ( dri_priv->textureSize == 0 ) {
screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;