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Author SHA1 Message Date
Emma Anholt
4aec44ea91 tu: Use appropriate chip variants for RB regs. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:06 +00:00
Emma Anholt
247a0389d6 tu: Use appropriate chip variants for A2D reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:05 +00:00
Emma Anholt
5d4598199e tu: Use appropriate chip variants for CONSERVATIVE_RAS_CNTL. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:05 +00:00
Emma Anholt
907dfeb732 tu: Use appropriate chip variants in PS setup. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:04 +00:00
Emma Anholt
b38bd7f868 tu: Use appopriate chip variants in SC scissor/viewport reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:04 +00:00
Emma Anholt
249680b508 tu: Use appropriate chip variants for SP_CS reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:03 +00:00
Emma Anholt
002fc56a0c tu: Use appropriate chip variants for VPC/PC reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:03 +00:00
Emma Anholt
8ed98f7429 tu: Use appropriate chip variants for SC_BIN_CNTL reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:02 +00:00
Emma Anholt
d335232fe5 tu: Use appropriate chip variants for VRS reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:01 +00:00
Emma Anholt
08782fbdc3 tu: Use appropriate chip variants for LRZ reg packing. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:01 +00:00
Emma Anholt
1f016974fa tu: Use appropriate chip variants for FOVEAT regs. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:00 +00:00
Emma Anholt
5a6bfc1614 tu: Use non-deprecated names for scratch regs. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:18:00 +00:00
Emma Anholt
f12a9b91c9 tu: Explicitly use 6XX scratch reg packing in perfcntrs_pass_cs_entries. 
It looks like this will change in 8xx, but for now this gets us off of
deprecated reg packing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:58 +00:00
Emma Anholt
454c665552 tu: Move tu6_emit_gs() to use reg packing. 
Gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:58 +00:00
Emma Anholt
56e63dc5ed tu: Move VPC_SO_FLUSH_BASE to use reg packing. 
Gets us the right reg on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:58 +00:00
Emma Anholt
4bc21cd77d tu: Convert tu_init_cmdbuf_start_a725_quirk() to non-deprecated packing. 
We can just pass 7xx as the CHIP, rather than templating.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:58 +00:00
Emma Anholt
a7ffdd31c5 tu: Template tu_pipeline_builder_parse_rasterization_order() by CHIP. 
This gets us the right reg on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:57 +00:00
Emma Anholt
fbcc32e990 tu: Template tu6_emit_vpc_varying_modes() by CHIP. 
This gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:57 +00:00
Emma Anholt
436f6059b4 tu: Template tu7_emit_subpass_shading_rate by CHIP. 
This gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:56 +00:00
Emma Anholt
99f31785a2 tu: Template tu6_emit_msaa() by CHIP. 
This gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:56 +00:00
Emma Anholt
22a8475151 tu: Template update_vsc_pipe by CHIP. 
This lets us use non-deprecated reg packing, and fixes incorrect emitting
of 0D08 on 6xx that was introduced in 0cf27a7236 ("tu: Clear
`VSC_UNKNOWN_0D08` on A7XX")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:55 +00:00
Emma Anholt
17e47f4dff tu: Template fdm_apply_store_coords() by CHIP. 
Gets the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:55 +00:00
Emma Anholt
339c3c7970 tu: Use non-deprecated reg packing in tu6_setup_streamout()'s CRBs. 
This gets us the right registers on a8xx.  We can clean this up later with
the CRB builder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:54 +00:00
Emma Anholt
7555600cc8 tu: Template tu_CmdBindIndexBuffer2KHR by CHIP. 
This gets us the right reg on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:54 +00:00
Emma Anholt
2f3ebc4f46 tu: Template tu_CmdBindTransformFeedbackBuffersEXT by CHIP. 
Gets the right regs for reg packing on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:54 +00:00
Emma Anholt
bfbc625f79 tu: Template tu_CmdBeginTransformFeedbackEXT() by CHIP. 
Gets the right regs for reg packing on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:53 +00:00
Emma Anholt
b69aa77456 tu: Template r2d_coords by CHIP. 
Gets us the right regs on 8xx

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:53 +00:00
Emma Anholt
b1a2757097 tu: Template tu7_emit_tile_render_begin_regs by CHIP. 
Gets us the right reg on 8xx

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:52 +00:00
Emma Anholt
e6a3699bf3 tu: Template tu6_build_depth_plane_z_mode by CHIP. 
Gets us the right reg on 8xx for GRAS_SU_DPETH_PLANE_CNTL.  I used a reg
pack function on the RB reg too, for consistency.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:52 +00:00
Emma Anholt
00bf0907e4 tu: Use tu_cs_emit_regs() for SU_POLY_OFFSET setup. 
This gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:51 +00:00
Emma Anholt
35e5be2bed tu: Template tu6_emit_rt_workaround() by CHIP. 
This lets us set the right registers on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:51 +00:00
Emma Anholt
4439101dd3 tu: Template tu6_emit_window_scissor by CHIP. 
This lets us set the right registers on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:50 +00:00
Emma Anholt
21e6c68bd1 tu: Use a register pack for VPC_PS_CNTL. 
Prep for dropping deprecated pack support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:50 +00:00
Yiwei Zhang
b42d7c3809 ci: uprev virglrenderer 
This brings in latest virglrenderer that supports recently added venus
extensions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38800>
 2025-12-04 21:38:54 +00:00
Aitor Camacho
273f668520 wsi/metal: Fix blit_imate_to_image's pool selection for cmd buffer alloc
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Fixes: 39a7d65113 ("wsi/metal: Backend addition for drivers built on top of Metal")

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38785>
 2025-12-04 20:08:02 +00:00
Aitor Camacho
a547c6306a wsi/metal: Fix command buffer release at destroy 
Fixes: 39a7d65113 ("wsi/metal: Backend addition for drivers built on top of Metal")

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38785>
 2025-12-04 20:08:02 +00:00
José Roberto de Souza
49adffb0c0 iris: Rename iris_binding_table::sizes to iris_binding_table::surf_count 
This better reflect the usage of this array.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
José Roberto de Souza
e551c8d302 iris: Move code to emit push constants to its own function 
This allow us to reduce a bit the size of iris_upload_dirty_render_state().

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
José Roberto de Souza
3dda6b05e0 iris: Improve iris_emit_binding_tables() 
Moving all 3 for loops into a single one and populating binding tables before
emit it, the last part has no side effect but when reading the code it makes
more sense to populate binding table then emit it.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
José Roberto de Souza
d4658ddb73 iris: Move code to emit binding tables to its own function 
This allow us to reduce a bit the size of iris_upload_dirty_render_state() and
in next patches some improvements to this new function will be done.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
Aitor Camacho
5b039e0996 kk: Expose more features/extensions we already support
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Extensions:
- VK_KHR_load_store_op_none
- VK_KHR_map_memory2
- VK_EXT_load_store_op_none

Features:
- fullDrawIndexUint32
- inheritedQueries
- shaderStorageImageExtendedFormats

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38783>
 2025-12-04 18:21:02 +00:00
Aitor Camacho
2e62777e0d kk: Apply robustness only when requested 
When lowering IO, we would always lower UBOs and SSBOs with robustness
enabled. This change only applies robustness if requested by the user.

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38784>
 2025-12-04 18:04:56 +00:00
Aitor Camacho
48555926ac kk: Guard writes after fragment demote 
Required for M1 and M2 chips since they don't demote fragments.

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38784>
 2025-12-04 18:04:56 +00:00
Emma Anholt
9e145f33cb ir3: Drop old comment about ldg vectorization limitation. 
We've looked at it again, and concluded that there's just no way that LDG
crossing a boundary could be OK in the components-are-read case but bad in
the components-are-not-read case, and this must have been papering over
something else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>
 2025-12-04 17:18:50 +00:00
Emma Anholt
24cd5088ca ir3: Perform vectorization on ldg/stg just like other memory access. 
shader-db effect comes from (perhaps older vkd3d?) DX12 fossils.  It sure
cleans up BDA CTS testcases, too.

Totals:
MaxWaves: 22151808 -> 22485222 (+1.51%); split: +1.51%, -0.06%
Instrs: 397754007 -> 396485642 (-0.32%); split: -0.41%, +0.10%
CodeSize: 990135656 -> 916286528 (-7.46%); split: -7.64%, +0.00%
STPs: 234296 -> 218861 (-6.59%); split: -6.62%, +0.03%
LDPs: 171664 -> 155386 (-9.48%); split: -9.53%, +0.04%

Totals from 130513 (8.36% of 1560788) affected shaders:
MaxWaves: 1376826 -> 1710240 (+24.22%); split: +24.30%, -0.90%
Instrs: 57789492 -> 56521127 (-2.19%); split: -2.84%, +0.66%
CodeSize: 256430400 -> 182581272 (-28.80%); split: -29.51%, +0.01%
NOPs: 7619148 -> 8015627 (+5.20%); split: -2.42%, +7.79%
MOVs: 4971200 -> 3968352 (-20.17%); split: -21.62%, +1.37%
COVs: 683166 -> 661427 (-3.18%); split: -3.24%, +0.04%
Full: 2422659 -> 1886993 (-22.11%); split: -22.98%, +0.03%
(ss): 1410724 -> 1479394 (+4.87%); split: -3.24%, +8.43%
(sy): 611391 -> 674588 (+10.34%); split: -1.14%, +11.66%
(ss)-stall: 4930898 -> 5265129 (+6.78%); split: -3.37%, +10.29%
(sy)-stall: 24138107 -> 29357000 (+21.62%); split: -1.82%, +23.71%
STPs: 112159 -> 96724 (-13.76%); split: -13.83%, +0.07%
LDPs: 113355 -> 97077 (-14.36%); split: -14.43%, +0.07%
Preamble Instrs: 83269073 -> 46493442 (-44.16%); split: -45.32%, +0.01%
Early Preamble: 79 -> 87 (+10.13%)
Cat0: 8516132 -> 8878083 (+4.25%); split: -2.28%, +6.68%
Cat1: 5994766 -> 4973985 (-17.03%); split: -19.02%, +1.94%
Cat2: 22297064 -> 22240177 (-0.26%); split: -0.30%, +0.05%
Cat3: 13748284 -> 13748279 (-0.00%)
Cat6: 1337948 -> 780266 (-41.68%); split: -42.19%, +0.27%
Cat7: 3247729 -> 3252768 (+0.16%); split: -1.48%, +1.71%
Subgroup size: 9280960 -> 9524224 (+2.62%); split: +2.63%, -0.01%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>
 2025-12-04 17:18:49 +00:00
Yogesh Mohan Marimuthu
f27b2b8d77 winsys/amdgpu,ac: get eop and csa size,alignment from kernel query
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:21 +00:00
Yogesh Mohan Marimuthu
f322bc8631 ac: update amdgpu_drm.h for uq metadata query info 
struct drm_amdgpu_info_uq_fw_areas is renamed to drm_amdgpu_info_uq_metadata.
query infor structure for compute and sdma is added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:20 +00:00
Samuel Pitoiset
b13003133d radv: add radv_cmd_state::emitted_rt_pipeline 
To stop abusing emitted_compute_pipeline for RT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset
7d4c49a271 radv: decouple RT and compute dispatches paths 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset
fa225de793 radv: constify radv_gfx12_emit_buffered_regs() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00