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tu: Use appropriate chip variants for VPC/PC reg packing.

Browse source 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
This commit is contained in:
Emma Anholt 2025-12-02 12:26:35 -08:00 • committed by Marge Bot
parent 8ed98f7429
commit 002fc56a0c
5 changed files with 23 additions and 24 deletions
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12
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -882,9 +882,9 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
tu6_emit_xs(cs, MESA_SHADER_VERTEX, vs, &pvtmem, vs_iova);
tu6_emit_xs(cs, MESA_SHADER_FRAGMENT, fs, &pvtmem, fs_iova);
tu_cs_emit_regs(cs, A6XX_PC_CNTL());
tu_cs_emit_regs(cs, PC_CNTL(CHIP));
if (CHIP == A7XX) {
tu_cs_emit_regs(cs, A7XX_VPC_PC_CNTL());
tu_cs_emit_regs(cs, VPC_PC_CNTL(CHIP));
}
tu6_emit_vpc<CHIP>(cs, vs, NULL, NULL, NULL, fs);
@ -894,8 +894,8 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
}
/* REPL_MODE for varying with RECTLIST (2 vertices only) */
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE_MODE(0, 0));
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_REPLACE_MODE_MODE(0, 2 << 2 | 1 << 0));
tu_cs_emit_regs(cs, VPC_VARYING_INTERP_MODE_MODE(CHIP, 0, 0));
tu_cs_emit_regs(cs, VPC_VARYING_REPLACE_MODE_MODE(CHIP, 0, 2 << 2 | 1 << 0));
tu6_emit_vs<CHIP>(cs, vs, 0);
tu6_emit_hs<CHIP>(cs, NULL);
@ -913,9 +913,9 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL(CHIP));
if (CHIP == A6XX) {
tu_cs_emit_regs(cs, A6XX_VPC_UNKNOWN_9107());
tu_cs_emit_regs(cs, VPC_UNKNOWN_9107(CHIP));
} else {
tu_cs_emit_regs(cs, A7XX_VPC_RAST_STREAM_CNTL_V2());
tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL_V2(CHIP));
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP,
.raster_mode = TYPE_TILED,

19
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -2010,10 +2010,10 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
tu_cs_emit_regs(cs, A6XX_VPC_REPLACE_MODE_CNTL(false));
tu_cs_emit_regs(cs, VPC_REPLACE_MODE_CNTL(CHIP, false));
tu_cs_emit_regs(cs, VPC_ROTATION_CNTL(CHIP));
tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(true));
tu_cs_emit_regs(cs, VPC_SO_OVERRIDE(CHIP, true));
tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_PS_SWIZZLE_CNTL, 0);
@ -2069,12 +2069,12 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
if (CHIP >= A7XX) {
/* Blob sets these two per draw. */
tu_cs_emit_regs(cs, A7XX_PC_HS_BUFFER_SIZE(TU_TESS_PARAM_SIZE));
tu_cs_emit_regs(cs, PC_HS_BUFFER_SIZE(CHIP, TU_TESS_PARAM_SIZE));
/* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
* but the meaning of this additional space is not known,
* so we play safe and don't add it.
*/
tu_cs_emit_regs(cs, A7XX_PC_TF_BUFFER_SIZE(TU_TESS_FACTOR_SIZE));
tu_cs_emit_regs(cs, PC_TF_BUFFER_SIZE(CHIP, TU_TESS_FACTOR_SIZE));
}
/* There is an optimization to skip executing draw states for draws with no
@ -5113,7 +5113,7 @@ tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
CP_COND_REG_EXEC_0_SYSMEM |
CP_COND_REG_EXEC_0_BINNING);
tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(true));
tu_cs_emit_regs(cs, VPC_SO_OVERRIDE(CHIP, true));
/* TODO: only flush buffers that need to be flushed */
for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
@ -7842,9 +7842,10 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT;
uint32_t primitive_cntl_0 =
A6XX_PC_CNTL(.primitive_restart = primitive_restart,
.provoking_vtx_last = provoking_vtx_last).value;
tu_cs_emit_regs(cs, A6XX_PC_CNTL(.dword = primitive_cntl_0));
PC_CNTL(CHIP, .primitive_restart = primitive_restart,
.provoking_vtx_last = provoking_vtx_last)
.value;
tu_cs_emit_regs(cs, PC_CNTL(CHIP, .dword = primitive_cntl_0));
if (CHIP == A7XX) {
tu_cs_emit_regs(cs, A7XX_VPC_PC_CNTL(.dword = primitive_cntl_0));
}
@ -7858,7 +7859,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
bool tess_upper_left_domain_origin =
(VkTessellationDomainOrigin)cmd->vk.dynamic_graphics_state.ts.domain_origin ==
VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
tu_cs_emit_regs(cs, A6XX_PC_DS_PARAM(
tu_cs_emit_regs(cs, PC_DS_PARAM(CHIP,
.spacing = tess_params->spacing,
.output = tess_upper_left_domain_origin ?
tess_params->output_upper_left :

10
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -3326,25 +3326,23 @@ tu6_emit_rast(struct tu_cs *cs,
enum a6xx_polygon_mode polygon_mode = tu6_polygon_mode(rs->polygon_mode);
tu_cs_emit_regs(cs,
A6XX_VPC_RAST_CNTL(polygon_mode));
tu_cs_emit_regs(cs, VPC_RAST_CNTL(CHIP, polygon_mode));
tu_cs_emit_regs(cs,
PC_DGEN_RAST_CNTL(CHIP, polygon_mode));
if (CHIP == A7XX || cs->device->physical_device->info->props.is_a702) {
tu_cs_emit_regs(cs,
A6XX_VPC_PS_RAST_CNTL(polygon_mode));
tu_cs_emit_regs(cs, VPC_PS_RAST_CNTL(CHIP, polygon_mode));
}
tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL(CHIP,
.stream = rs->rasterization_stream,
.discard = rs->rasterizer_discard_enable));
if (CHIP == A6XX) {
tu_cs_emit_regs(cs, A6XX_VPC_UNKNOWN_9107(
tu_cs_emit_regs(cs, VPC_UNKNOWN_9107(CHIP,
.raster_discard = rs->rasterizer_discard_enable));
} else {
tu_cs_emit_regs(cs, A7XX_VPC_RAST_STREAM_CNTL_V2(
tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL_V2(CHIP,
.stream = rs->rasterization_stream,
.discard = rs->rasterizer_discard_enable));

4
src/freedreno/vulkan/tu_query_pool.cc
View file

@ -1327,7 +1327,7 @@ emit_begin_xfb_query(struct tu_cmd_buffer *cmdbuf,
struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
uint64_t begin_iova = primitive_query_iova(pool, query, begin, 0, 0);
tu_cs_emit_regs(cs, A6XX_VPC_SO_QUERY_BASE(.qword = begin_iova));
tu_cs_emit_regs(cs, VPC_SO_QUERY_BASE(CHIP, .qword = begin_iova));
tu_emit_event_write<CHIP>(cmdbuf, cs, FD_WRITE_PRIMITIVE_COUNTS);
if (!cmdbuf->state.pass)
@ -1860,7 +1860,7 @@ emit_end_xfb_query(struct tu_cmd_buffer *cmdbuf,
if (!cmdbuf->state.pass)
cmdbuf->state.xfb_query_running_before_rp = false;
tu_cs_emit_regs(cs, A6XX_VPC_SO_QUERY_BASE(.qword = end_iova));
tu_cs_emit_regs(cs, VPC_SO_QUERY_BASE(CHIP, .qword = end_iova));
tu_emit_event_write<CHIP>(cmdbuf, cs, FD_WRITE_PRIMITIVE_COUNTS);
tu_cs_emit_wfi(cs);

2
src/freedreno/vulkan/tu_shader.cc
View file

@ -2327,7 +2327,7 @@ tu6_emit_fs(struct tu_cs *cs,
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CNTL_6, 1);
tu_cs_emit(cs, COND(fs && fs->reads_primid, A6XX_VFD_CNTL_6_PRIMID4PSEN));
tu_cs_emit_regs(cs, A6XX_PC_PS_CNTL(.primitiveiden = fs && fs->reads_primid));
tu_cs_emit_regs(cs, PC_PS_CNTL(CHIP, .primitiveiden = fs && fs->reads_primid));
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, GRAS_MODE_CNTL(CHIP, 0x2));