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tu: Move VPC_SO_FLUSH_BASE to use reg packing.

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Gets us the right reg on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
This commit is contained in:
Emma Anholt 2025-12-02 15:58:59 -08:00 • committed by Marge Bot
parent 4bc21cd77d
commit 56e63dc5ed
1 changed files with 1 additions and 2 deletions
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3
src/freedreno/vulkan/tu_cmd_buffer.cc
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@ -5118,8 +5118,7 @@ tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
/* TODO: only flush buffers that need to be flushed */
for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
/* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
tu_cs_emit_qw(cs, global_iova_arr(cmd, flush_base, i));
tu_cs_emit_regs(cs, VPC_SO_FLUSH_BASE(CHIP, i, .qword = global_iova_arr(cmd, flush_base, i)));
tu_emit_event_write<CHIP>(cmd, cs, (enum fd_gpu_event) (FD_FLUSH_SO_0 + i));
}