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tu: Use non-deprecated reg packing in tu6_setup_streamout()'s CRBs.

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This gets us the right registers on a8xx.  We can clean this up later with
the CRB builder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
This commit is contained in:
Emma Anholt 2025-12-02 17:08:50 -08:00 • committed by Marge Bot
parent 7555600cc8
commit 339c3c7970
1 changed files with 12 additions and 13 deletions
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25
src/freedreno/vulkan/tu_pipeline.cc
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@ -505,9 +505,9 @@ tu6_setup_streamout(struct tu_cs *cs,
sizedw += 2;
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, sizedw);
tu_cs_emit(cs, REG_A6XX_VPC_SO_MAPPING_WPTR);
tu_cs_emit(cs, VPC_SO_MAPPING_WPTR(CHIP).reg);
tu_cs_emit(cs, 0);
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
tu_cs_emit(cs, VPC_SO_CNTL(CHIP).reg);
tu_cs_emit(cs, 0);
if (has_pc_dgen_so_cntl) {
@ -567,18 +567,17 @@ tu6_setup_streamout(struct tu_cs *cs,
prog_count += 1;
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 10 + 2 * prog_count);
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
tu_cs_emit(cs, A6XX_VPC_SO_CNTL_STREAM_ENABLE(info->streams_written) |
COND(info->stride[0] > 0,
A6XX_VPC_SO_CNTL_BUF0_STREAM(1 + info->buffer_to_stream[0])) |
COND(info->stride[1] > 0,
A6XX_VPC_SO_CNTL_BUF1_STREAM(1 + info->buffer_to_stream[1])) |
COND(info->stride[2] > 0,
A6XX_VPC_SO_CNTL_BUF2_STREAM(1 + info->buffer_to_stream[2])) |
COND(info->stride[3] > 0,
A6XX_VPC_SO_CNTL_BUF3_STREAM(1 + info->buffer_to_stream[3])));
fd_reg_pair reg = VPC_SO_CNTL(
CHIP,
.buf0_stream = info->stride[0] > 0 ? 1 + info->buffer_to_stream[0] : 0,
.buf1_stream = info->stride[1] > 0 ? 1 + info->buffer_to_stream[1] : 0,
.buf2_stream = info->stride[2] > 0 ? 1 + info->buffer_to_stream[2] : 0,
.buf3_stream = info->stride[3] > 0 ? 1 + info->buffer_to_stream[3] : 0,
.stream_enable = info->streams_written);
tu_cs_emit(cs, reg.reg);
tu_cs_emit(cs, reg.value);
for (uint32_t i = 0; i < 4; i++) {
tu_cs_emit(cs, REG_A6XX_VPC_SO_BUFFER_STRIDE(i));
tu_cs_emit(cs, VPC_SO_BUFFER_STRIDE(CHIP, i).reg);
tu_cs_emit(cs, info->stride[i]);
}
bool first = true;