Commit graph

7390 commits

Author SHA1 Message Date
Connor Abbott
49d29d4f10 ir3: Use correct immediate size for constlen calculation
Some checks are pending
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"size" is the allocated size of the array, not the number of immediates
actually used. We could wind up returning a too-large constlen, larger
than 512, and since the binning variant uses the non-binning variant's
constlen as it's max_const we could make binning variants use c512.x and
crash when encoding.

Fixes: 86f3c0c4c2 ("ir3: simplify constlen calculation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40961>
2026-04-16 05:40:14 +00:00
Connor Abbott
280c64d720 ir3: Don't reset immediate count to 0 after lowering
We need to know the immediate count even after lowering, to compute the
overall const size. Previously we were using the capacity field, but
that's unreliable and won't be available once we switch to a real
dynamic array container instead of (poorly) reinventing one.

Fixes: 86f3c0c4c2 ("ir3: simplify constlen calculation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40961>
2026-04-16 05:40:14 +00:00
Zan Dobersek
4d4a951ac6 fd: add a8xx perfcntr countables
Add the a8xx perfcntr countables lists for each supported perfcntr group,
as collected from the proprietary profiling tools.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40971>
2026-04-15 14:09:24 +00:00
Job Noorman
118b975ce7 ir3: use ldg.k load size
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
ldg.k can copy up to 256 vec4s at once but we currently emit one ldg.k
per vec4. Fix this by using the load size field of ldg.k.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:01 +00:00
Job Noorman
a1272cabe0 ir3/isa: fix load size encoding for ldg.k
The load size field starts at b23 instead of b24 and is 8 bits in size.
b23 makes the blob disassembler select between interpreting the load
size as an immediate or a GPR. However, using a GPR doesn't work as the
HW still seems to interpret the field as an immediate. We copy the
blob's behavior here for consistency.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:01 +00:00
Job Noorman
e6529b54c0 ir3: add support for the ldg.k a1.x addressing mode
We assumed a1.x addressing doesn't work. However, it turns out it
actually does work but instead of taking the offset's hight bits from
a1.x and adding an immediate to the low bits, the full offset is stored
in a1.x and the offset is ignored.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:01 +00:00
Job Noorman
bf167ca73b ir3: allow shared address src for ldg.k
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40947>
2026-04-15 07:58:00 +00:00
Job Noorman
ce810bb19b ir3/parser: add @constlen header
Constlen cannot always be derived from the usage of @const et al. For
example when using ldc.k/ldg.k. Add a @constlen header to explicitly set
it.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40940>
2026-04-15 06:46:10 +00:00
Job Noorman
0e95730be0 ir3/parser: set constlen when adding const regs
Since we don't set constlen anymore based on static const reg usage,
computerator was broken. Fix this by setting constlen for @const et al.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 4e456ebde4 ("ir3/collect_info: remove max_const calculation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40940>
2026-04-15 06:46:09 +00:00
Job Noorman
4808037f6e ir3/legalize: track need_ss/sy_for_const per const reg
Instead of tracking if *any* const reg has been written since the last
sync, use a bitset to track exactly which const regs have been written.
This often helps us prevent stalls.

Preamble stats:

Totals from 32893 (18.66% of 176258) affected shaders:
Instrs: 3540796 -> 3540370 (-0.01%); split: -0.08%, +0.07%
CodeSize: 30635588 -> 30627370 (-0.03%); split: -0.09%, +0.07%
NOPs: 491600 -> 491174 (-0.09%); split: -0.58%, +0.49%
(ss): 465746 -> 450057 (-3.37%); split: -3.54%, +0.17%
(sy): 89251 -> 85497 (-4.21%); split: -4.30%, +0.09%
(ss)-stall: 1210233 -> 1164381 (-3.79%); split: -4.44%, +0.66%
(sy)-stall: 1286176 -> 1283034 (-0.24%); split: -0.94%, +0.70%
Cat0: 594508 -> 594082 (-0.07%); split: -0.48%, +0.41%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40954>
2026-04-15 06:20:56 +00:00
Job Noorman
c1bf9d6fd5 ir3: set cat6.dst_offset for ldc
Not needed by the assembler but this allows us to track the const reg
destination in ir3.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40954>
2026-04-15 06:20:56 +00:00
Job Noorman
b730dff54e ir3/postsched: update legalize state for terminators
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Terminators might need sync flags/delays and hence have an effect on
scheduling decisions.

Totals from 13218 (7.50% of 176258) affected shaders:
Instrs: 12241764 -> 12237098 (-0.04%); split: -0.14%, +0.10%
CodeSize: 23483966 -> 23479174 (-0.02%); split: -0.08%, +0.06%
NOPs: 2594291 -> 2589625 (-0.18%); split: -0.67%, +0.49%
(ss): 381711 -> 381252 (-0.12%); split: -0.41%, +0.29%
(sy): 167625 -> 165596 (-1.21%); split: -1.21%, +0.00%
(ss)-stall: 1645060 -> 1615134 (-1.82%); split: -2.11%, +0.29%
(sy)-stall: 4920750 -> 4835994 (-1.72%); split: -1.89%, +0.17%
Preamble Instrs: 2478730 -> 2478732 (+0.00%); split: -0.00%, +0.00%
Cat0: 2881982 -> 2877316 (-0.16%); split: -0.60%, +0.44%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40952>
2026-04-15 05:57:17 +00:00
Sergi Blanch Torne
8d7ab8ba6d ci: nightly run xfiles for a618 angle job
It may be related with !37802

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40599>
2026-04-14 20:34:52 +00:00
Rhys Perry
a6b86d43d3 ir3/ra: fix copy-paste error
I don't entirely understand what this is all doing, but this looks like a
copy-paste error.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40480>
2026-04-13 22:28:15 +00:00
Rhys Perry
54af9431d1 ir3/array_to_ssa: initialize ir3_instruction::data
This should have already been NULL because this looks like the first time
this field is used, but that's a bit fragile.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40480>
2026-04-13 22:28:15 +00:00
Rhys Perry
4f0fb5784f ir3/array_to_ssa: skip remove_trivial_phi for non-array phis
remove_trivial_phi() mostly does nothing for non-array phis, but it
rewrites sources if their definining instruction are trivial phis.

In the case of trivial phis in the loop continue block (for loops with
divergent non-trivial continues), we might need to keep those if they
write a shared register, because the source of the trivial phi will not be
reachable from the loop header phi.

In this example, the predecessors of the continue block should be block2,
but the physical predecessors are block2 and block3, requiring a phi in
the continue block which will then be lowered by ir3_lower_shared_phis.
loop {
   block1:
   a = phi 0, b
   if (divergent) {
      block2:
      b = a + 1
      continue;
   }
   block3:
   break;
}

Fixes RA validation error when compiling blackmythwukong/5645a84e669a6179
from radv_fossils.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40480>
2026-04-13 22:28:15 +00:00
Job Noorman
4e456ebde4 ir3/collect_info: remove max_const calculation
constlen is now directly calculated from the const allocations; no need
to infer it from const reg usage anymore.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40929>
2026-04-13 19:15:59 +00:00
Job Noorman
c7e7d68912 ir3: remove unused ir3_context::has_relative_load_const_ir3
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40929>
2026-04-13 19:15:59 +00:00
Job Noorman
86f3c0c4c2 ir3: simplify constlen calculation
Instead of inferring constlen from the usage of const registers by
various instructions, we can calculate it directly from the const file
allocations. This greatly simplifies the calculation of constlen.

Note that the increase in constlen comes from a few binning variants.
This doesn't matter as the constlen of the corresponding non-binning
variant is used for those anyway.

Totals from 73 (0.04% of 176258) affected shaders:
Constlen: 3428 -> 3720 (+8.52%)

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40929>
2026-04-13 19:15:59 +00:00
Job Noorman
3a076beb13 ir3/analyze_ubo_ranges: don't over-align consts when loaded via preamble
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Consts don't need to be const_upload_unit aligned when initialized in
the preamble.

Totals from 121136 (68.73% of 176258) affected shaders:
MaxWaves: 1731152 -> 1731238 (+0.00%); split: +0.01%, -0.01%
Instrs: 41003924 -> 41006922 (+0.01%); split: -0.04%, +0.04%
CodeSize: 83451224 -> 84153136 (+0.84%); split: -0.15%, +0.99%
NOPs: 6920243 -> 6923031 (+0.04%); split: -0.20%, +0.24%
MOVs: 1202942 -> 1203260 (+0.03%); split: -0.13%, +0.16%
COVs: 654863 -> 654827 (-0.01%); split: -0.01%, +0.00%
Full: 1356271 -> 1356003 (-0.02%); split: -0.03%, +0.01%
(ss): 1019993 -> 1019657 (-0.03%); split: -0.16%, +0.12%
(sy): 489430 -> 489607 (+0.04%); split: -0.07%, +0.10%
(ss)-stall: 3878805 -> 3875997 (-0.07%); split: -0.21%, +0.13%
(sy)-stall: 14655425 -> 14660516 (+0.03%); split: -0.08%, +0.11%
STPs: 9680 -> 9653 (-0.28%)
LDPs: 17026 -> 16999 (-0.16%)
Preamble Instrs: 8805343 -> 9195550 (+4.43%); split: -1.65%, +6.08%
Early Preamble: 101798 -> 103143 (+1.32%); split: +1.44%, -0.12%
Constlen: 5761784 -> 4356540 (-24.39%); split: -24.40%, +0.02%
Subgroup size: 832 -> 1664 (+100.00%)
Cat0: 7631222 -> 7634040 (+0.04%); split: -0.18%, +0.22%
Cat1: 1897357 -> 1897579 (+0.01%); split: -0.09%, +0.10%
Cat2: 15537632 -> 15537426 (-0.00%); split: -0.00%, +0.00%
Cat6: 424903 -> 424996 (+0.02%); split: -0.00%, +0.02%
Cat7: 1002957 -> 1003028 (+0.01%); split: -0.07%, +0.08%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40908>
2026-04-13 15:38:31 +00:00
Job Noorman
f2d4529494 ir3/analyze_ubo_ranges: add const_align_vec4 helper
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40908>
2026-04-13 15:38:31 +00:00
Danylo Piliaiev
889f71f71a tu: Add tracepoints for clear/copy/blit/lrz ops
There shouldn't be many per frame, so it won't be spammy.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40788>
2026-04-13 11:29:48 +00:00
Danylo Piliaiev
9e56c7bd8f tu: Support transfer commands for R64 formats
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
CTS tests that require transfer commands:
   dEQP-VK.robustness.*r64*
   dEQP-VK.api.image_clearing.*.r64*
   dEQP-VK.image.extend_operands_spirv1p4.r64_*
   dEQP-VK.image.nontemporal_operand.r64_*
   dEQP-VK.image.queue_transfer.*.r64_

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Danylo Piliaiev
5b87bbfad3 tu: Support EXT_shader_image_atomic_int64
Required for SM6.6 in vkd3d-proton and used in a number of UE5 titles.
From descriptor side R64 images are R32G32_UINT, and to get storage_descriptor
we have to move early-return if format doesn't support rendering after
storage_descriptor setup.

Passes vkd3d-proton test:
test_shader_sm66_64bit_atomics

CTS tests:
dEQP-VK.image.atomic_operations.*.r64*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
0eab11b67f ir3: add support for 64-bit image atomics
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
b7b66d3efd ir3: add support for r64u?i image loads/stores
Add a NIR pass to lower these to r32g32u loads/stores, which is our
descriptor format.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
bc4edc79dd ir3: support isam with less than 4 components
This currently doesn't happen yet but we want to support load_image with
lass than 4 components in the future.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
bd69573c34 ir3: allow imm src0 (IBO) on bindless atomics
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Collabora's Gfx CI Team
d15e4274f6 Uprev Piglit to 11ce9eb56edb00e6a7702d13168cc827ce5e0cbd
d0a16eee4f...11ce9eb56e

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40427>
2026-04-10 21:21:52 +00:00
Karmjit Mahil
718f90dd8c tu: Remove unecessary forward declaration
tu_queue.h is included so this isn't necessary.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:55:01 +00:00
Karmjit Mahil
0fcecb97f1 tu: Cleanup some includes
Remove unused includes or heavy includes (e.g. `tu_common.h`) when
we could have done with lighter ones.

iwyu was used to find these cases.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:55:01 +00:00
Karmjit Mahil
9429b474f6 tu: Reorder includes
These follow our clang-format style now.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:55:01 +00:00
Karmjit Mahil
ef0de29292 tu: Update .clang-format include categories
Add missing folder patterns, and make the `^<vulkan/` pattern
apply to system includes too, so that all system includes are
in one group.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:55:00 +00:00
Karmjit Mahil
3c9ce4fdbc tu: Undef before redefining MESA_LOG_TAG
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:55:00 +00:00
Karmjit Mahil
bd66b7bc01 tu: Use "nir/" for the nir includes
This is to match the pattern used in our clang-format file

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:55:00 +00:00
Karmjit Mahil
cd299b433e freedreno: Add check_xml_includes to meson setup
This avoids wasting CI time by catching the error early. We do
still need the meson test to catch these issues locally when
rebuilding from an already configured build directory though.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:54:59 +00:00
Karmjit Mahil
1208d84f3c freedreno: Add check_xml_includes test
Add a test to ensure that we're always using one of the wrapper
files instead of including the XML generated headers directly.

Assisted-by: Opencode (MiniMax M2.7)
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:54:59 +00:00
Karmjit Mahil
396201a9ab freedreno: Add fd{2,3,4,5}_hw.h and fd_hw_common.h
Add some wrapper header files so that we always include everything
that's needed by the generated header. This is in preparation for
setting up a script which enforces using these instead of importing
the xml generated headers directly.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:54:59 +00:00
Karmjit Mahil
35f6efac76 freedreno/a6xx: Add missing include to fd6_pack.h
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:54:59 +00:00
Karmjit Mahil
b6ddd10d21 freedreno/registers: Add some missing include in fd6_hw.h
The generated header can't be used stand-alone so add the includes
in fd6_hw.h

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40853>
2026-04-10 13:54:59 +00:00
Alexander Koskovich
f560760b27 freedreno/common: add support for the Adreno 810
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Add support for the Adreno 810 found on the SM7635 (milos).

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40613>
2026-04-10 01:24:59 +00:00
Connor Abbott
82b3db7e06 tu: Enable multiviewGeometryShader
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Connor Abbott
73ab56fd2e tu: Lower maxMultiviewViewCount to 6
With multiview, the HW has to dispatch at least ViewCount * 6 fibers per
primitive, since there are up to 6 VS threads per primitive. The HW can
launch multiple GS waves per VS wave but one VS wave must contain the
entire primitive. With ViewCount = 16 there are 96 fibers per
primitive, which is more than we can launch in one wave. To fix this,
lower the maximum view count.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Connor Abbott
3433e53da7 tu: Fill GS/DS ViewID register fields
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Connor Abbott
f497e3913b tu: Adjust multiview lowering for GS
When there is a GS, run multiview lowering for the VS and multiply the
per-primitive varying stride by the view count since all outputs are now
per-view.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Connor Abbott
be84cb6211 ir3: Support multiview in GS lowering
With GS+multiview, the VS will loop over each view in the shader while
each GS invocation only corresponds to a single view. Varyings for each
view will be stored next to each other in local memory. Implement view
index calculations when lowering VS outputs/GS inputs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Connor Abbott
bc72ef2ee9 ir3: Implement ViewIndex for GS
For GS, the ViewIndex is passed through from the DS/VS in a
similar manner to PrimID.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Connor Abbott
2d4bb4cdc6 freedreno: Name GS/DS ViewID register fields
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40153>
2026-04-09 20:34:58 +00:00
Dhruv Mark Collins
46aac5abaf tu: Only emit preempt optimization ambles when active
This avoid unnecessarily emitting the switch back/away ambles when
they aren't actually used due to preemption optimization being
disabled. This alleviates unnecessary overhead when not running with
the mitigation for kernel drivers which support it.

Signed-off-by: Dhruv Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40852>
2026-04-09 17:29:18 +00:00
Dhruv Mark Collins
18437c7a65 tu: Disable features using performance counter for KGSL
KGSL doesn't support reading of performance counters by writing to
the selector registers directly from a userspace CS, instead these
requests need to be routed via the KGSL uAPI for perf counters.

Certain Turnip features which use performance counters such as
KHR_performance_query as well as preempt-optimize mode in autotune
are now explicitly disabled to reflect this.

Signed-off-by: Dhruv Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40852>
2026-04-09 17:29:18 +00:00