Commit graph

23654 commits

Author SHA1 Message Date
Jose Fonseca
09d6243aed gallivm: Workaround LLVM PR23628.
Temporarily undefine DEBUG macro while including LLVM C++ headers,
leveraging the push/pop_macro pragmas, which are supported both by GCC
and MSVC.

https://bugs.freedesktop.org/show_bug.cgi?id=90621

Trivial.
2015-05-28 10:12:55 +01:00
Eric Anholt
10aacf5ae8 vc4: Just stream out fallback IB contents.
The idea I had when I wrote the original shadow code was that you'd see a
set_index_buffer to the IB, then a bunch of draws out of it.  What's
actually happening in openarena is that set_index_buffer occurs at every
draw, so we end up making a new shadow BO every time, and converting more
of the BO than is actually used in the draw.

While I could maybe come up with a better caching scheme, for now just
do the simple thing that doesn't result in a new shadow IB allocation
per draw.

Improves performance of isosurf in drawelements mode by 58.7967% +/-
3.86152% (n=8).
2015-05-27 17:29:11 -07:00
Eric Anholt
f8de6277bf vc4: Don't try to put our dmabuf-exported BOs into the BO cache.
We'd sometimes try to reallocate something that X was using as a new
pipe_resource, and potentially conflict in our rendering.  But even
worse, if we reallocated the BO as a shader, the kernel would reject
rendering using the shader.
2015-05-27 17:29:11 -07:00
Eric Anholt
b0edc19a52 vc4: Don't forget to make our raster shadow textures non-raster.
Not sure what happened in my testing that made the previous shadow
code fix glxgears swapbuffering, but this also fixes lots of CopyArea
in X (like dragging xlogo around in metacity).
2015-05-27 17:29:11 -07:00
Samuel Pitoiset
41630c0653 vc4: make vc4_begin_query() return a boolean
I forgot to make the change in 96f164f6f0.
This fixes a warning with GCC and probably an error with Clang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-05-27 17:29:03 -07:00
Vinson Lee
147ffd4816 gallivm: Do not use NoFramePointerElim with LLVM 3.7.
TargetOptions::NoFramePointerElim was removed in llvm-3.7.0svn r238244
"Remove NoFramePointerElim and NoFramePointerElimOverride from
TargetOptions and remove ExecutionEngine's dependence on CodeGen. NFC."

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2015-05-27 17:01:51 -07:00
EdB
40665362fd clover: Log build options when dumping clc source.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-05-27 15:33:58 +03:00
Brian Paul
eec904d29c xlib: fix X_GLXCreateContextAtrribs/Attribs typo
In case the glproto.h file isn't up to date, we provide the #define
for X_GLXCreateContextAttribsARB.

v2: fix other occurances, improve #ifndef test, per Jose.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-05-26 09:58:09 -06:00
Marek Olšák
224a77cc60 radeonsi: use a switch statement in si_delete_shader_selector
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-05-26 12:42:37 +02:00
Marek Olšák
0c5a309cee radeonsi: use a switch statement in si_shader_selector_key
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-05-26 12:42:37 +02:00
Marek Olšák
fa7f606e89 radeonsi: fix scratch buffer setup for geometry shaders
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-05-26 12:42:37 +02:00
Marek Olšák
f41517242a radeonsi: remove unused cases from si_shader_io_get_unique_index
These can't occur between VS and GS, because GS is only supported
in the core profile.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-05-26 12:42:37 +02:00
Marek Olšák
af4b9c7c2e radeonsi: don't count special outputs for the VS export count
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-05-26 12:42:36 +02:00
Marek Olšák
e4339bc988 radeonsi: add support for PIPE_CAP_TGSI_TEXCOORD
Without it, texcoords are mapped to GENERIC[0..7], PointCoord is mapped to
GENERIC[8], and user-defined varyings start from GENERIC[9]. Since texcoords
can only be used between VS and PS, and PointCoord is PS-only, it's silly to
always start from GENERIC[9] in all other shaders (such as LS, HS, ES, GS).

This adds support for TEXCOORD and PCOORD semantics. As a result, st/mesa
will use GENERIC[0] as a base for user-defined varyings, which should make
linking ES and GS as well as tessellation shaders at runtime easier.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-05-26 12:42:31 +02:00
Marek Olšák
3d35027fdc tgsi/ureg: enable creating tessellation shaders with ureg_create_shader
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-26 11:46:28 +02:00
Marek Olšák
c1266f28d6 tgsi/text: enable parsing tessellation shaders
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-26 11:46:28 +02:00
Marek Olšák
0d84b6cf84 gallium: rename TGSI tessellation processor types to match pipe shader names
I forgot to do this when pushing the interface changes.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-26 11:46:28 +02:00
Marek Olšák
92c31bb0dd gallium: use const in set_tess_state
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-26 11:46:28 +02:00
Koop Mast
967825d053 clover: Build fix for FreeBSD.
Cc: 10.6 10.5 <mesa-stable@lists.freedesktop.org>
2015-05-26 11:46:28 +02:00
Ilia Mirkin
3ec1815285 nv30: falling back to draw path for edgeflag does no good
The problem is that the EDGEFLAG has to be toggled at vertex submission
time. This can be done from either the draw or the regular paths. Avoid
falling back to draw just because there's an edgeflag.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 21:45:31 -04:00
Ilia Mirkin
25be70462d nv30/draw: switch varying hookup logic to know about texcoords
Commit 8acaf862df switched things over to use TEXCOORD instead of
GENERIC, but did not update the nv30 swtnl draw paths. This teaches the
draw logic about TEXCOORD.

Among other things, this fixes a crash in demos/arbocclude when using
swtnl. Curiously enough, the point-sprite piglit works without this.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 21:45:31 -04:00
Ilia Mirkin
c3d36a2e1a nv30/draw: allocate vertex buffers in gart
These are only used once per draw, so it makes sense to keep them in
GART. Also take this opportunity to modernize the buffer mapping API
usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 21:45:22 -04:00
Ilia Mirkin
fdad7dfbda nv30/draw: only use the DMA1 object (GART) if the bo is not in VRAM
Instead of always having it in the data, let the bo placement decide it.
This fixes glxgears with swtnl forced on.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 21:45:08 -04:00
Ilia Mirkin
3600439897 nv30/draw: fix indexed draws with swtnl path and a resource index buffer
The map = assignment was missing.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 20:16:51 -04:00
Roland Scheidegger
6a111e54d7 llvmpipe: (trivial) add parantheses in (!x == y) expression
Apparently some compilers think we probably wanted to do !(x == y) instead
and issue a warning, so just shut it up... No functional change, obviously.

Cc: <mesa-stable@lists.freedesktop.org>
2015-05-25 22:24:42 +02:00
Ilia Mirkin
147816375d nv30/draw: draw expects constbuf size in bytes, not vec4 units
This fixes glxgears with NV30_SWTNL=1 forced on. Probably fixes a bunch
of other situations where we fall back to the swtnl path.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 14:11:16 -04:00
Ilia Mirkin
89585edf3c nv30/draw: avoid leaving stale pointers in draw state
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-25 14:11:16 -04:00
Ilia Mirkin
7518fc3c66 nv30: fix clip plane uploads and enable changes
nv30_validate_clip depends on the rasterizer state. Also we should
upload all the new clip planes on change since next time the plane data
won't have changed, but the enables might.

This fixes fixed-clip-enables and vs-clip-vertex-enables shader tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-24 12:00:03 -04:00
Ilia Mirkin
aba3392541 nv30: avoid doing extra work on clear and hitting unexpected states
Clearing can happen at a time when various state objects are incoherent
and not ready for a draw. Some of the validation functions don't handle
this well, so only flush the framebuffer state. This has the advantage
of also not doing extra work.

This works around some crashes that can happen when clearing.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
2015-05-24 12:00:03 -04:00
Ilia Mirkin
9870ed05dd nv30: avoid leaking render state and draw shaders
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-24 02:26:29 -04:00
Ilia Mirkin
605ce36d7f nv30: don't leak fragprog consts
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-24 01:33:06 -04:00
Ilia Mirkin
fa7f9f123b nv50/ir: avoid messing up arg1 of PFETCH
There can be scenarios where the "indirect" arg of a PFETCH becomes
known, and so the code will attempt to propagate it. Use this
opportunity to just fold it into the first argument, and prevent the
load propagation pass from touching PFETCH further.

This fixes gs-input-array-vec4-index-rd.shader_test and
vs-output-array-vec4-index-wr-before-gs.shader_test on nvc0 at least.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-23 22:15:15 -04:00
Grigori Goronzy
f972b223c4 clover: try userptr for CL_MEM_USE_HOST_PTR
According to spec, CL_MEM_USE_HOST_PTR should directly use host memory,
if possible. This is just what userptr is for, so use it.

In case the memory cannot be mapped, a fallback similar to
CL_MEM_COPY_HOST_PTR is used.

v2: constify, drop unneeded cast

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-05-24 01:14:49 +02:00
Grigori Goronzy
5c495e8638 clover: implement CL_MEM_ALLOC_HOST_PTR
This flag is typically used to request pinned host memory, to avoid
any copies between GPU and CPU.

This improves throughput with an older OpenCL app which I unfortunately
can't publish due to its licensing.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-05-24 01:14:48 +02:00
Ilia Mirkin
c922758685 nv30: check nouveau_bo_map output of notify bo
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-23 19:10:07 -04:00
Ilia Mirkin
921917c8d8 nvc0: a geometry shader can have up to 1024 vertices output
The 1024 is already reported everywhere, not sure where this 0x1ff came
from.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-23 17:55:21 -04:00
Samuel Pitoiset
c783fd476c nv50: fix PIPE_QUERY_TIMESTAMP_DISJOINT, based on nvc0
PIPE_QUERY_TIMESTAMP_DISJOINT could not work because q->ready was always
set to FALSE. To fix this issue, add more different states for queries
according to nvc0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-23 19:00:55 +02:00
Ilia Mirkin
217301843a nvc0/ir: LOAD's can't be used for shader inputs
We forgot to convert to VFETCH in case of indirect access. Fix that.

This avoids crashes on the new gs-input-array-vec4-index-rd and
vs-output-array-vec4-index-wr-before-gs but they still fail.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-22 19:08:24 -04:00
Ilia Mirkin
0bab3962f5 nv50/ir: guess that the constant offset is the starting slot of array
When we get something like IN[ADDR[0].x+5], we will now guess that we
should look at IN[5] for the "base" information.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-22 19:08:14 -04:00
Ilia Mirkin
d1eea18a59 nvc0/ir: set ftz when sources are floats, not just destinations
In the case of a compare, the destination might be a predicate, but we
still want to flush denorms.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-05-22 16:51:05 -04:00
Ilia Mirkin
a85aba190d nv50/ir: allow OP_SET to merge with OP_SET_AND/etc as well as a neg
This covers the pattern where a KILL_IF is used, which triggers a
comparison of -x to 0. This can usually be folded into the comparison whose
result is being compared to 0, however it may, itself, have already been
combined with another comparison. That shouldn't impact the logic of
this pass however. With this and the & 1.0 change, code like

00000020: 001c0001 80081df4     set b32 $r0 lt f32 $r0 0x3e800000
00000028: 001c0000 201fc000     and b32 $r0 $r0 0x3f800000
00000030: 7f9c001e dd885c00     set $p0 0x1 lt f32 neg $r0 0x0
00000038: 0000003c 19800000     $p0 discard

becomes

00000020: 001c001d b5881df4     set $p0 0x1 lt f32 $r0 0x3e800000
00000028: 0000003c 19800000     $p0 discard

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-22 16:51:05 -04:00
Ilia Mirkin
d2a474e8d4 nvc0/ir: optimize set & 1.0 to produce boolean-float sets
This has started to happen more now that the backend is producing
KILL_IF more often.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
2015-05-22 16:51:05 -04:00
Ilia Mirkin
e5ad19a46e nvc0/ir: allow iset to produce a boolean float
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-22 16:51:05 -04:00
Ilia Mirkin
0ec6b8ea8c nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-22 16:51:05 -04:00
Samuel Pitoiset
a21d23e191 nv50: fix PIPELINE_STATISTICS with HUD, based on nvc0
Tested on NVA8. No regression for ARB_pipeline_statistics piglit tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-22 11:39:23 +02:00
Samuel Pitoiset
867fd2b5f5 nv50: fix 64-bit queries with HUD, based on nvc0
A sequence number is written for 32-bits queries to make sure they are
ready, but not for 64-bits queries. Instead, we have to use a fence in
order to fix the HUD because it doesn't wait until the result is ready.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-22 11:39:23 +02:00
Christian König
6921ea42a1 radeon/vce: adapt new firmware interface changes
v2: make this also compatible with original released firmware
v3 (chk): switch to original idea of separate files for fw versions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2)
2015-05-22 10:17:24 +02:00
Christian König
2b40c306d2 radeon/vce: move CPB handling function into common code
They are not firmware version dependent.

Signed-off-by: Christian König <christian.koenig@amd.com>
2015-05-22 10:17:24 +02:00
Dave Airlie
7c1a00174b u_math: uses assert, include assert.h
this fixes a build problem found on RHEL s390.

not sure what configure options caused it, I couldn't get it on
x86 here.

Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.6" mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-05-22 09:19:58 +10:00
Ilia Mirkin
6cdb29d52f freedreno/a3xx: set .zw of sprite coords to .01
Fixes non-determinism in bin/point-sprite rendering, and the stars on
the intro screen to neverball.

Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-05-20 21:54:00 -04:00