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radeonsi: add support for PIPE_CAP_TGSI_TEXCOORD

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Without it, texcoords are mapped to GENERIC[0..7], PointCoord is mapped to
GENERIC[8], and user-defined varyings start from GENERIC[9]. Since texcoords
can only be used between VS and PS, and PointCoord is PS-only, it's silly to
always start from GENERIC[9] in all other shaders (such as LS, HS, ES, GS).

This adds support for TEXCOORD and PCOORD semantics. As a result, st/mesa
will use GENERIC[0] as a base for user-defined varyings, which should make
linking ES and GS as well as tessellation shaders at runtime easier.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2015-05-09 19:36:17 +02:00
parent 3d35027fdc
commit e4339bc988
4 changed files with 13 additions and 15 deletions
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2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -251,6 +251,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_TGSI_TEXCOORD:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@ -286,7 +287,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:

1
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -1183,6 +1183,7 @@ handle_semantic:
continue;
case TGSI_SEMANTIC_PRIMID:
case TGSI_SEMANTIC_FOG:
case TGSI_SEMANTIC_TEXCOORD:
case TGSI_SEMANTIC_GENERIC:
target = V_008DFC_SQ_EXP_PARAM + param_count;
shader->vs_output_param_offset[i] = param_count;

20
src/gallium/drivers/radeonsi/si_state.c
View file

@ -636,18 +636,14 @@ static void *si_create_rs_state(struct pipe_context *ctx,
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 12.0f;
tmp = S_0286D4_FLAT_SHADE_ENA(1);
if (state->sprite_coord_enable) {
tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
}
}
si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
S_0286D4_FLAT_SHADE_ENA(1) |
S_0286D4_PNT_SPRITE_ENA(1) |
S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
/* point size 12.4 fixed point */
tmp = (unsigned)(state->point_size * 8.0);

5
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -661,8 +661,9 @@ bcolor:
(interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
tmp |= S_028644_FLAT_SHADE(1);
if (name == TGSI_SEMANTIC_GENERIC &&
sctx->sprite_coord_enable & (1 << index)) {
if (name == TGSI_SEMANTIC_PCOORD ||
(name == TGSI_SEMANTIC_TEXCOORD &&
sctx->sprite_coord_enable & (1 << index))) {
tmp |= S_028644_PT_SPRITE_TEX(1);
}