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86322 commits

Author SHA1 Message Date
Ben Widawsky
3b0c2bc417 i965/gen9: Add HiZ auxiliary buffer support
The original functionality this patch introduces was authored by a patch from
Ken (the commit subject was the same). Since I ended up changing so many patches
in the code before this one, I had some non-trivial decisions to make, and I
didn't feel it was appropriate to keeps Ken's name as author (mostly because he
might not like what I've done). Ken's original patch was like 2 LOC :-)

In either case, some credit needs to go to Ken, and to Jordan for a few small
other changes in that original patch.

v2: Back to a smaller diff now that ISL handles most of the actual
    programming (Lionel)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-11-08 16:13:57 +00:00
Jordan Justen
c0f505c7ef i965: Add function to indicate when sampling with hiz is supported
Currently it indicates that this is never supported, but soon it will
be supported for gen8+^w gen9+

v2 by Ben:
- Explicitly disable aux_hiz for gen < 9 (with comment)
- squashed in next patch to avoid unused and useless functions

   i965: Support sampling with hiz during rendering

   For gen8, we can sample from depth while using the hiz buffer. This
   allows us to sample depth without resolving from hiz to the depth
   texture.

   To do this we must resolve to hiz before drawing so we can use the hiz
   buffer to sample while rendering. Hopefully the hiz buffer will
   already be resolved in most cases because it was previously rendered,
   meaning the hiz resolve is a no-op.

   Note that this is still controlled by the
   intel_miptree_sample_with_hiz function, and we will enable hiz
   sampling for gen8 in a separate patch.

   Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
   Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-11-08 16:13:57 +00:00
Ben Widawsky
c53e9c9780 i965/miptree: Create a hiz mcs type
This seems counter to the goal of consolidating hiz, mcs, and later ccs buffers.
Unfortunately, hiz on gen6 is a thing the code supports, and this wart will be
helpful to achieve that. Overall, I believe it does help unify AUX buffers on
gen7+.

I updated the size field which I introduced in the previous patch, even though
we have no use for it.

XXX: As I mentioned in the last patch, the height given to the MCS buffer
allocation in intel_miptree_alloc_mcs() looks wrong, but I don't claim to fully
understand how the MCS buffer is laid out.

v2: rebase on master (Lionel)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-11-08 16:13:57 +00:00
Ben Widawsky
36d1c555ed i965: Drop the aux mt when not used
This patch will preserve the BO & offset, and not the miptree for the
aux_mcs buffer. Eventually it might make sense to pull put the sizing
function in miptree creation, but for now this should be sufficient
and not too hideous.

v2: Save BO's offset too (Lionel)

v3: Squash previous patch storing the size of the allocated aux buffer
    (Lionel)
    Fix memory leak with mcs_buf->bo (Lionel)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-11-08 16:13:57 +00:00
Ben Widawsky
42db7ab179 i965/miptree: Directly gtt map the mcs buffer
The next patch will change the map type, and this will make sure there are no
regressions as a result of the other stuff. Since the miptree is newly created,
I believe it is always safe to just map.

It is possible to CPU map this buffer on LLC platforms (it additionally requires
rounding up to tile size). I did experiment with that patch, and found no
performance gains to be had.

I've added in error handling while here. Generally GTT mapping is an operation
which is highly unlikely to fail, but we may as well handle it when it does.

v2: rebase on master (Lionel)

v3: print out error if gtt mapping fails (Topi)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-11-08 16:13:57 +00:00
Jordan Justen
0041169cac i965: Wrap MCS miptree in intel_miptree_aux_buffer
This will allow us to treat HiZ and MCS the same when using as an
auxiliary surface buffer.

v2: (Ben) Minor rebase conflict resolution.
   Rename mcs_buf to aux_buf to address upcoming change for hiz specific buffers.
   That second thing is essentially a squash of:
   i965/gen8: Use intel_miptree_aux_buffer for auxiliary buffer - which didn't need
   to be separate in my opinion.

v3: rebase on master (Lionel)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>a (v2)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v3)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-11-08 16:13:57 +00:00
Nicolai Hähnle
88f791db75 gallivm: fix [IU]MUL_HI regression
This patch does two things:

1. It separates the host-CPU code generation from the generic code
   generation. This guards against accidently breaking things for
   radeonsi in the future.

2. It makes sure we actually use both arguments and don't just compute
   a square :-p

Fixes a regression introduced by commit 29279f44b3

Cc: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-11-08 16:25:54 +01:00
Roland Scheidegger
3fa10ffb49 draw: use vectorized calculations for fetch
Instead of doing all the math with scalars, use vectors. This means the
overflow math needs to be done manually, albeit that's only really
problematic for the stride/index mul, the rest has been pretty much
moved outside the shader loop (albeit the mul could actually be optimized
away too), where things are still scalar. Because llvm is complete fail
with the zero-extend widening mul, roll our own even...
To eliminate control flow in the main shader loop fetch, provide fake
buffers (so index 0 is always valid to fetch).
Still uses aos fetch though in the end - mostly because some more code
would be needed to handle unaligned fetches in that path, and because for
most formats it won't make a difference anyway (we generate some truly
horrendous code for things like R16G16_something for instance).

Instanced fetch however stays roughly the same as before, except that
no longer the same element is fetched multiple times (I've seen a reduction
of ~3 times in main shader loop size due to apparently llvm not being able
to deduce it's really all the same with a couple instanced elements).

Also, for elts gathering, use vectorized code as well - provide a fake
elt buffer if there's no valid one bound.

The generated shaders are smaller and faster to compile (not entirely sure
about execution speed, but generally unless there's just single vertices
to handle I would expect it to be faster - there's more opportunities
for future improvements by using soa fetch).

No piglit change.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-11-08 03:41:26 +01:00
Roland Scheidegger
29279f44b3 gallivm: introduce 32x32->64bit lp_build_mul_32_lohi function
This is used by shader umul_hi/imul_hi functions (and soon by draw).
It's actually useful separating this out on its own, however the real
reason for doing it is because we're using an optimized sse2 version,
since the code llvm generates is atrocious (since there's no widening
mul in llvm, and it does not recognize the widening mul pattern, so
it generates code for real 64x64->64bit mul, which the cpu can't do
natively, in contrast to 32x32->64bit mul which it could do).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-11-08 03:41:26 +01:00
Anuj Phogat
b0554c25e7 i965: Add space before paren
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-11-07 16:13:57 -08:00
Anuj Phogat
501d608e56 i965: Remove unnecessary white space
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-11-07 16:13:57 -08:00
Anuj Phogat
329ae922bd i965: Fix alpha-to-coverage and alpha test enabled checks
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2016-11-07 16:13:02 -08:00
Anuj Phogat
a1bd2f6950 mesa: Add helper function _mesa_is_alpha_to_coverage_enabled()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2016-11-07 16:13:02 -08:00
Anuj Phogat
0295c792b4 mesa: Add helper function _mesa_is_alpha_test_enabled()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2016-11-07 16:13:02 -08:00
Anuj Phogat
7fed07766d mesa: Use separate line for function return type
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2016-11-07 16:13:02 -08:00
Samuel Pitoiset
e32e5d214e nvc0: simplify draw parameters upload for vertex shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-11-07 22:50:17 +01:00
Steven Toth
381edca826 gallium/hud: protect against and initialization race
In the event that multiple threads attempt to install a graph
concurrently, protect the shared list.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-07 18:31:52 +01:00
Steven Toth
5a58323064 gallium/hud: close a previously opened handle
We're missing the closedir() to the matching opendir().

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-07 18:31:52 +01:00
Steven Toth
6ffed08679 gallium/hud: fix a problem where objects are free'd while in use.
Instead of trying to maintain a reference counted list of valid HUD
objects, and freeing them accordingly, creating race conditions
between unanticipated multiple threads, simply accept they're
allocated once and never released until the process terminates.

They're a shared resource between multiple threads, so accept
they're always available for use.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-07 18:31:52 +01:00
Rob Clark
a5e733c6b5 mesa: drop current draw/read buffer when ctx is released
This fixes a problem seen with gallium drivers vs android wallpaper.
Basically, what happens is:

   EGLSurface tmpSurface = mEgl.eglCreatePbufferSurface(mEglDisplay, mEglConfig, attribs);
   mEgl.eglMakeCurrent(mEglDisplay, tmpSurface, tmpSurface, mEglContext);

   int[] maxSize = new int[1];
   Rect frame = surfaceHolder.getSurfaceFrame();
   glGetIntegerv(GL_MAX_TEXTURE_SIZE, maxSize, 0);

   mEgl.eglMakeCurrent(mEglDisplay, EGL_NO_SURFACE, EGL_NO_SURFACE, EGL_NO_CONTEXT);
   mEgl.eglDestroySurface(mEglDisplay, tmpSurface);

   ... check maxSize vs frame size and bail if needed ...

   mEglSurface = mEgl.eglCreateWindowSurface(mEglDisplay, mEglConfig, surfaceHolder, null);
   ... error checking ...
   mEgl.eglMakeCurrent(mEglDisplay, mEglSurface, mEglSurface, mEglContext);

When the window-surface is created, it ends up with the same ptr address
as the recently freed tmpSurface pbuffer surface.  Which after many
levels of indirection, results in st_framebuffer_validate() ending up with
the same/old framebuffer object, and in the end never calling the
DRIimageLoaderExtension::getBuffers().  Then in droid_swap_buffers(), the
dri2_surf is still the old pbuffer surface (with dri2_surf->buffer being
NULL, obviously, so when wallpaper app calls eglSwapBuffers() nothing
gets enqueued to the compositor).  Resulting in a black/blank background
layer.

Note that at the EGL layer, when the context is unbound, EGL drops it's
references to the draw and read buffer as well.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Tested-by: Robert Foss <robert.foss@collabora.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
2016-11-07 10:23:26 -05:00
Serge Martin
cc495055cd clover: Add CL_PROGRAM_BINARY_TYPE support (CL1.2).
v3 [Francisco Jerez]: Loosely based on Serge's v1 of this patch in
   order to avoid CL-specific enums in the clover module binary
   format.  In addition to other changes made in v2: Represent the CL
   program binary type as the section type instead of adding a CL
   API-specific enum, check that the binary types of the input objects
   are valid during clLinkProgram(), pass section type as argument to
   build_module_library() instead of using separate function.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-11-06 15:56:54 +01:00
Serge Martin
05fcc73f08 clover: add missing clGetDeviceInfo CL1.2 queries
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2016-11-06 15:56:49 +01:00
Samuel Pitoiset
8cc4a74971 nvc0: get rid of NVE4_COMPUTE_MP_PM_{A,B}_SIGSEL_XXX
Instead, hardcode group sigsel because there are a bunch of unknown
groups, especially on SM50/SM52.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-11-05 19:28:25 +01:00
Samuel Pitoiset
a295364596 gm107/ir: emit RED instead of ATOM when no dst
This is similar to NVC0 and GK110 emitters where we emit
reduction operations instead of atomic operations when the
destination is not used.

Found after writing some tests which check if performance counters
return the expected value. In that case, gred_count returned 0
on gm107 while at least gk106 returned the correct value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-11-05 19:27:35 +01:00
Brian Paul
cfb5a9ab23 st/mesa: initialize members of glsl_to_tgsi_instruction in emit_asm()
This fixes random crashes with MSVC release builds.  It seems the
members are implicitly initialized to zero with gcc, but not MSVC.
In particular, the tex_offset_num_offset field was non-zero causing
a loop over the NULL tex_offsets array to crash.

Zero-init those fields and a few others to be safe.

The regression began with acc23b04cf "ralloc: remove memset from
ralloc_size".

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-11-05 12:09:40 -06:00
Mauro Rossi
0148313ea3 android: amd/common: add support for libmesa_amd_common
Fixes the following building error introduced with commit 7115e56
and related amd/common dependencies:

external/mesa/src/gallium/drivers/radeonsi/si_shader.c:6861: error: undefined reference to 'ac_is_sgpr_param'
external/mesa/src/gallium/drivers/radeonsi/si_shader.c:6951: error: undefined reference to 'ac_is_sgpr_param'
clang++: error: linker command failed with exit code 1 (use -v to see invocation)

ninja: build stopped: subcommand failed.
build/core/ninja.mk:148: recipe for target 'ninja_wrapper' failed
make: *** [ninja_wrapper] Error 1

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-11-05 18:42:29 +01:00
Marek Olšák
0f72f7292a winsys/radeon: don't call surface_best for FMASK
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98518

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-11-05 18:36:26 +01:00
Kenneth Graunke
0c17b0b6f0 mesa: Add linear ETC2/EAC to the compressed format list with ES3 compat.
GL_ARB_ES3_compatibility brings ETC2/EAC formats to desktop GL.

The meaning of the GL compressed format list is pretty vague - it's
supposed to return formats for "general-purpose usage".  (GL 4.2
deprecates the list because of this.)  Basically everyone interprets
this as "linear RGB/RGBA".

ETC2/EAC meets that criteria, so while we shouldn't be required to add
it to the list, there's also little harm in doing so, at least on
platforms with native support.  I doubt anyone is using this list for
much anyway, so even on platforms without native support, it's probably
not a big deal.

Makes the following GL45-CTS.gtf43 tests pass:

* GL3Tests.eac_compression_r11.gl_compressed_r11_eac
* GL3Tests.eac_compression_rg11.gl_compressed_rg11_eac
* GL3Tests.eac_compression_signed_r11.gl_compressed_signed_r11_eac
* GL3Tests.eac_compression_signed_rg11.gl_compressed_signed_rg11_eac
* GL3Tests.etc2_compression_rgb8.gl_compressed_rgb8_etc2
* GL3Tests.etc2_compression_rgb8_pt_alpha1.gl_compressed_rgb8_pt_alpha1_etc2
* GL3Tests.etc2_compression_rgba8.gl_compressed_rgba8_etc2

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-11-04 16:10:20 -07:00
Eric Anholt
283d4d18e5 vc4: Use Newton-Raphson on the 1/W write to fix glmark2 terrain.
The 1/W was apparently not accurate enough, and we were getting sparklies
in the distance.  The closed driver also did a N-R step here.

Cc: <mesa-stable@lists.freedesktop.org>
2016-11-04 15:34:38 -07:00
Eric Anholt
70fc3a941a vc4: Make sure that vertex shader texture2D() calls use LOD 0.
I noticed this while trying to debug glmark2 terrain (which does vertex
shader texturing, but no mipmaps on its textures sampled from the VS).
2016-11-04 15:34:38 -07:00
Nicolai Hähnle
2c875158e2 radeonsi: fix vertex fetches for 2_10_10_10 formats
The hardware always treats the alpha channel as unsigned, so add a shader
workaround. This is rare enough that we'll just build a monolithic vertex
shader.

The SINT case cannot actually happen in OpenGL, but I've included it for
completeness since it's just a mix of the other cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-11-04 21:30:18 +01:00
Nicolai Hähnle
322483f71b st/mesa: fix the layer of VDPAU surface samplers
A (latent) bug in VDPAU interop was exposed by commit
e5cc84dd43.

Before that commit, the st_vdpau code created samplers with
first_layer == last_layer == 1 that the general texture handling code
would immediately delete and re-create, because the layer does not match
the information in the GL texture object.

This was correct behavior at least in the DMABUF case, because the imported
resource is supposed to have the correct offset already applied.  In the
non-DMABUF case, this was just plain wrong but apparently nobody noticed.

After that commit, the state tracker assumes that an existing sampler is
correct at all times.  Existing samplers are supposed to be deleted when
they may become invalid, and they will be created on-demand.  This meant
that the sampler with first_layer == last_layer == 1 stuck around, leading
to rendering artefacts (on radeonsi), command stream failures (on r600), and
assertions (in debug builds everywhere).

This patch fixes the problem by simply not creating a sampler at all in
st_vdpau_map_surface.  We rely on the generic texture code to do the right
thing, adding the layer_override to make the non-DMABUF case work.

v2: add the layer_override

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98512
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Cc: Christian König <deathsimple@vodafone.de>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-11-04 21:26:29 +01:00
Dave Airlie
d0d5f7600c Revert "st/vdpau: use linear layout for output surfaces"
This reverts commit d180de3532.

This is a radeon specific hack that causes problems on nouveau
when combined with the SHARED flag later. If radeonsi needs a fix
for this, please fix it in the driver.

[chk]
Using linear surfaces for this makes sense because tilling isn't
beneficial and the surfaces can potentially be shared with other GPUs
using the VDPAU OpenGL interop.

[airlied]
I think we need a flag that isn't SHARED/LINEAR that is more
SHARED_OTHER_GPU.

[mareko]
Does radeonsi need PIPE_BIND_VIDEO_DECODE_OUTPUT that it would translate
into linear ?

[mareko]
My only concern is decoding performance. If the decoder works in 64x1
blocks, tiling will hurt. That's the theory. I don't know how the
decoder works.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> (I+A)
2016-11-04 15:04:21 +00:00
Marek Olšák
00baaa4752 radeonsi: fix an assertion failure in si_decompress_sampler_color_textures
This fixes a crash in Deus Ex: Mankind Divided. Release builds were
unaffected, so it's not too serious.

Cc: 11.2 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-04 11:30:47 +01:00
Marek Olšák
64c2593a5c glx: make interop ABI visible again
This was broken when the GLAPI use was removed from mesa_glinterop.h.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-11-04 11:30:47 +01:00
Marek Olšák
ee39d4456e egl: make interop ABI visible again
This was broken when the GLAPI use was removed from mesa_glinterop.h.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-11-04 11:30:47 +01:00
Marek Olšák
bf51b45313 egl: use util/macros.h
I need the definition of PUBLIC.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-11-04 11:30:47 +01:00
Nicolai Hähnle
84a74be9e4 radeonsi: enable GLSL 4.50
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-11-04 10:33:50 +01:00
Nicolai Hähnle
e4b378800e st/glsl_to_tgsi: fix dvec[34] loads from SSBO
When splitting up loads, we have to add 16 bytes to the offset for
the high components, just like already happens for stores.

Fixes arb_gpu_shader_fp64@shader_storage@layout-std140-fp64-shader.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-11-04 10:31:02 +01:00
Nicolai Hähnle
aef7eb4cac glsl/cache: correct asprintf error handling
From the manpage of asprintf:

   "If memory allocation wasn't possible, or some other error occurs,
    these functions will return -1, and the contents of strp are
    undefined."

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-11-04 10:28:08 +01:00
Michel Dänzer
8ce7ef75f5 gallium/radeon: Multiply bpe by nsamples in surf_winsys_to_drm
For symmetry with surf_drm_to_winsys.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-11-04 16:51:18 +09:00
Michel Dänzer
356458363d gallium/radeon: Use flags parameter in radeon_winsys_surface_init
Fixes valgrind warnings about surf_ws->flags being uninitialized while
starting X.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-04 16:49:39 +09:00
Michel Dänzer
6f844a30c1 gallium/radeon: Only convert stencil info if RADEON_SURF_SBUFFER is set
Fixes valgrind warnings about using uninitialized memory when starting X.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-11-04 16:48:59 +09:00
Michel Dänzer
38fb9aa1aa gallium/radeon: Only loop up to last_level for drm<->winsys conversion
Fixes spurious assertion failure in surf_level_drm_to_winsys when
starting X, due to processing a miplevel which was never initialized.

Fixes: e9c76eeeaa ("gallium/radeon: remove radeon_surf_level::pitch_bytes")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-11-04 16:47:43 +09:00
Tapani Pälli
1e3f7bfc9a anv: use limits.h instead of deprecated/obsolete values.h
Mesa uses limits.h elsewhere, and this makes is possible to
compile anv_allocator.c on Android.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2016-11-04 08:35:43 +02:00
Eric Anholt
80157466cd vc4: Add miptree/texture state support for ETC1 compressed textures.
The format isn't flagged as enabled at runtime yet, because we need kernel
validation support.
2016-11-03 18:42:58 -07:00
Eric Anholt
bedb996087 vc4: Fix use of undefined values since the ralloc zeroing changes.
reralloc() no longer zeroes the new contents, so switch to using
rzalloc_array() instead.
2016-11-03 18:42:58 -07:00
Eric Anholt
49936364e4 nir: Make sure to set the texsrc type in nir drawpixels/bitmap lowering.
We were leaving an undefined value since the ralloc zeroing changes.
Fixes nir_validate() failures on vc4.

v2: Fix the color-index case of drawpixels as well.

Reviewed-by: Rob Clark <robdclark@gmail.com> (v1)
2016-11-03 18:42:58 -07:00
Roland Scheidegger
572a952126 draw: fix undefined input handling some more...
Previous fixes were incomplete - some code still iterated through the number
of elements provided by velem layout instead of the number stored in the key
(which is the same as the number defined by the vs). And also actually
accessed the elements from the layout directly instead of those in the key.
This mismatch could still cause crashes.
(Besides, it is a very good idea to only use data stored in the key anyway.)
v2: move null format check, remove now unnecessary function parameter,
some minor prettify

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-04 01:48:22 +01:00
Brian Paul
f4dd3bde37 gallium/hud: call fflush() after printing error messages
For Windows.  Otherwise, we don't see the message until the program exits.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-11-03 14:29:23 -06:00