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gallium/radeon: remove radeon_surf_level::pitch_bytes

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-26 18:48:36 +02:00
parent c66a550385
commit e9c76eeeaa
13 changed files with 48 additions and 44 deletions
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4
src/gallium/drivers/r600/evergreen_state.c
View file

@ -3492,8 +3492,8 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;

4
src/gallium/drivers/r600/r600_state.c
View file

@ -2947,8 +2947,8 @@ static void r600_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;

29
src/gallium/drivers/radeon/r600_texture.c
View file

@ -182,8 +182,9 @@ static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned leve
{
return rtex->surface.level[level].offset +
box->z * rtex->surface.level[level].slice_size +
box->y / rtex->surface.blk_h * rtex->surface.level[level].pitch_bytes +
box->x / rtex->surface.blk_w * rtex->surface.bpe;
(box->y / rtex->surface.blk_h *
rtex->surface.level[level].nblk_x +
box->x / rtex->surface.blk_w) * rtex->surface.bpe;
}
static int r600_init_surface(struct r600_common_screen *rscreen,
@ -259,12 +260,12 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
return r;
}
if (pitch_in_bytes_override && pitch_in_bytes_override != surface->level[0].pitch_bytes) {
if (pitch_in_bytes_override &&
pitch_in_bytes_override != surface->level[0].nblk_x * bpe) {
/* old ddx on evergreen over estimate alignment for 1d, only 1 level
* for those
*/
surface->level[0].nblk_x = pitch_in_bytes_override / bpe;
surface->level[0].pitch_bytes = pitch_in_bytes_override;
surface->level[0].slice_size = pitch_in_bytes_override * surface->level[0].nblk_y;
}
@ -291,7 +292,7 @@ static void r600_texture_init_metadata(struct r600_texture *rtex,
metadata->tile_split = surface->tile_split;
metadata->mtilea = surface->mtilea;
metadata->num_banks = surface->num_banks;
metadata->stride = surface->level[0].pitch_bytes;
metadata->stride = surface->level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
}
@ -548,7 +549,8 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
}
return rscreen->ws->buffer_get_handle(res->buf,
rtex->surface.level[0].pitch_bytes,
rtex->surface.level[0].nblk_x *
rtex->surface.bpe,
rtex->surface.level[0].offset,
rtex->surface.level[0].slice_size,
whandle);
@ -945,7 +947,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"pitch_bytes=%u, mode=%u, tiling_index = %u\n",
"mode=%u, tiling_index = %u\n",
i, rtex->surface.level[i].offset,
rtex->surface.level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
@ -953,7 +955,6 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.level[i].nblk_x,
rtex->surface.level[i].nblk_y,
rtex->surface.level[i].pitch_bytes,
rtex->surface.level[i].mode,
rtex->surface.tiling_index[i]);
@ -964,7 +965,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"pitch_bytes=%u, mode=%u, tiling_index = %u\n",
"mode=%u, tiling_index = %u\n",
i, rtex->surface.stencil_level[i].offset,
rtex->surface.stencil_level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
@ -972,7 +973,6 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.stencil_level[i].nblk_x,
rtex->surface.stencil_level[i].nblk_y,
rtex->surface.stencil_level[i].pitch_bytes,
rtex->surface.stencil_level[i].mode,
rtex->surface.stencil_tiling_index[i]);
}
@ -1547,7 +1547,8 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
offset = r600_texture_get_offset(staging_depth, level, box);
}
trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
trans->transfer.stride = staging_depth->surface.level[level].nblk_x *
staging_depth->surface.bpe;
trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
trans->staging = (struct r600_resource*)staging_depth;
buf = trans->staging;
@ -1568,7 +1569,8 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
return NULL;
}
trans->staging = &staging->resource;
trans->transfer.stride = staging->surface.level[0].pitch_bytes;
trans->transfer.stride = staging->surface.level[0].nblk_x *
staging->surface.bpe;
trans->transfer.layer_stride = staging->surface.level[0].slice_size;
if (usage & PIPE_TRANSFER_READ)
@ -1579,7 +1581,8 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
buf = trans->staging;
} else {
/* the resource is mapped directly */
trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
trans->transfer.stride = rtex->surface.level[level].nblk_x *
rtex->surface.bpe;
trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
offset = r600_texture_get_offset(rtex, level, box);
buf = &rtex->resource;

2
src/gallium/drivers/radeon/radeon_uvd.c
View file

@ -1353,7 +1353,7 @@ static unsigned bank_wh(unsigned bankwh)
void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
struct radeon_surf *chroma)
{
msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe;
switch (luma->level[0].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;

4
src/gallium/drivers/radeon/radeon_vce.c
View file

@ -223,7 +223,7 @@ struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
signed *luma_offset, signed *chroma_offset)
{
unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
unsigned pitch = align(enc->luma->level[0].nblk_x * enc->luma->bpe, 128);
unsigned vpitch = align(enc->luma->level[0].nblk_y, 16);
unsigned fsize = pitch * (vpitch + vpitch / 2);
@ -454,7 +454,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
goto error;
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
cpb_size = align(tmp_surf->level[0].nblk_x * tmp_surf->bpe, 128);
cpb_size = cpb_size * align(tmp_surf->level[0].nblk_y, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;

8
src/gallium/drivers/radeon/radeon_vce_40_2_2.c
View file

@ -94,8 +94,8 @@ static void create(struct rvce_encoder *enc)
RVCE_CS(0x00000000); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
RVCE_CS(enc->luma->level[0].pitch_bytes); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encRefPicChromaPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(0x00000000); // encRefPic(Addr|Array)Mode, encPicStructRestriction, disableRDO
RVCE_END();
@ -324,8 +324,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode
RVCE_CS(0x00000000); // encInputPicTileConfig
RVCE_CS(enc->pic.picture_type); // encPicType

4
src/gallium/drivers/radeon/radeon_vce_50.c
View file

@ -131,8 +131,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
if (enc->dual_pipe)
RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
else

8
src/gallium/drivers/radeon/radeon_vce_52.c
View file

@ -177,8 +177,8 @@ static void create(struct rvce_encoder *enc)
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
RVCE_CS(enc->luma->level[0].pitch_bytes); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encRefPicChromaPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants);
@ -244,8 +244,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
if (enc->dual_pipe)
enc->enc_pic.eo.enc_input_pic_addr_array_disable2pipe_disablemboffload = 0x00000000;
else

1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -281,7 +281,6 @@ struct radeon_surf_level {
uint64_t dcc_fast_clear_size;
uint16_t nblk_x;
uint16_t nblk_y;
uint32_t pitch_bytes;
enum radeon_surf_mode mode;
};

4
src/gallium/drivers/radeonsi/cik_sdma.c
View file

@ -134,8 +134,8 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
unsigned dst_pitch = rdst->surface.level[dst_level].pitch_bytes / bpp;
unsigned src_pitch = rsrc->surface.level[src_level].pitch_bytes / bpp;
unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x;
unsigned src_pitch = rsrc->surface.level[src_level].nblk_x;
uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,

4
src/gallium/drivers/radeonsi/si_dma.c
View file

@ -232,8 +232,8 @@ static void si_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);

1
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -191,7 +191,6 @@ static int compute_level(struct amdgpu_winsys *ws,
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;

19
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View file

@ -67,25 +67,27 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
}
static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
const struct radeon_surf_level *level_ws)
const struct radeon_surf_level *level_ws,
unsigned bpe)
{
level_drm->offset = level_ws->offset;
level_drm->slice_size = level_ws->slice_size;
level_drm->nblk_x = level_ws->nblk_x;
level_drm->nblk_y = level_ws->nblk_y;
level_drm->pitch_bytes = level_ws->pitch_bytes;
level_drm->pitch_bytes = level_ws->nblk_x * bpe;
level_drm->mode = level_ws->mode;
}
static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
const struct radeon_surface_level *level_drm)
const struct radeon_surface_level *level_drm,
unsigned bpe)
{
level_ws->offset = level_drm->offset;
level_ws->slice_size = level_drm->slice_size;
level_ws->nblk_x = level_drm->nblk_x;
level_ws->nblk_y = level_drm->nblk_y;
level_ws->pitch_bytes = level_drm->pitch_bytes;
level_ws->mode = level_drm->mode;
assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
}
static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
@ -156,9 +158,9 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i], bpe);
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->stencil_level[i]);
&surf_ws->stencil_level[i], bpe);
surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
@ -190,9 +192,10 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i],
surf_drm->bpe * surf_drm->nsamples);
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
&surf_drm->stencil_level[i]);
&surf_drm->stencil_level[i], surf_drm->nsamples);
surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];