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st/glsl_to_tgsi: fix dvec[34] loads from SSBO

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When splitting up loads, we have to add 16 bytes to the offset for
the high components, just like already happens for stores.

Fixes arb_gpu_shader_fp64@shader_storage@layout-std140-fp64-shader.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2016-11-03 11:00:36 +01:00
parent aef7eb4cac
commit e4b378800e
1 changed files with 4 additions and 6 deletions
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10
src/mesa/state_tracker/st_glsl_to_tgsi.cpp
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@ -774,9 +774,9 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
int i = u_bit_scan(&writemask);
/* before emitting the instruction, see if we have to adjust store
/* before emitting the instruction, see if we have to adjust load / store
* address */
if (i > 1 && inst->op == TGSI_OPCODE_STORE &&
if (i > 1 && (inst->op == TGSI_OPCODE_LOAD || inst->op == TGSI_OPCODE_STORE) &&
addr.file == PROGRAM_UNDEFINED) {
/* We have to advance the buffer address by 16 */
addr = get_temp(glsl_type::uint_type);
@ -784,7 +784,6 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
inst->src[0], st_src_reg_for_int(16));
}
/* first time use previous instruction */
if (dinst == NULL) {
dinst = inst;
@ -804,11 +803,10 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
dinst->dst[j].index = initial_dst_idx[j];
if (i > 1) {
if (dinst->op == TGSI_OPCODE_STORE) {
if (dinst->op == TGSI_OPCODE_LOAD || dinst->op == TGSI_OPCODE_STORE)
dinst->src[0] = addr;
} else {
if (dinst->op != TGSI_OPCODE_STORE)
dinst->dst[j].index++;
}
}
} else {
/* if we aren't writing to a double, just get the bit of the initial writemask