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Author SHA1 Message Date
Cooper Yuan
3a3c7fd52e functions declaration with 'extern' 2009-06-22 15:10:57 +08:00
Cooper Yuan
2f6451042d Pass viewport id to r700SendViewportState function, otherwise the radom value may beyond R700_MAX_VIEWPORTS 2009-06-22 14:33:18 +08:00
Cooper Yuan
46ca8e5782 add LINK_STATES for SPI_PS and SEMANTIC 2009-06-22 10:16:01 +08:00
Alex Deucher
1036ef2bf4 Merge master and fix conflicts 2009-06-12 12:09:34 -04:00
Jakob Bornecrantz
1cd0afffc9 progs/rbug: Add binary to bmp converter program 2009-06-12 15:07:57 +01:00
Jakob Bornecrantz
3fff84a999 Merge branch 'mesa_7_5_branch' 2009-06-12 12:31:04 +01:00
Jakob Bornecrantz
c6de08fff4 mesa: Enable uploads of only depth to z24s8 textures 2009-06-12 12:29:02 +01:00
Owen W. Taylor
279143c6e8 Disable SGI_swap_control extension for DRI2 
We currently don't have support for SGI_swap_control for direct
contexts with DRI2, so disable reporting the extension. Reporting
the extension, and then having glXSwapIntervalSGI() "succeed"
but do nothing can confuse applications.

https://bugs.freedesktop.org/show_bug.cgi?id=22123
 2009-06-12 11:41:37 +10:00
Dave Airlie
d0fab94842 radeon: fix size of mipmap texture array 2009-06-12 11:37:13 +10:00
Dave Airlie
a5d92d7ed2 radeon/r200/r300: fix max texture levels assert 
use the actual value set in the context
 2009-06-12 11:35:10 +10:00
Dave Airlie
7f223ff891 Merge remote branch 'main/radeon-rewrite' 2009-06-12 11:17:32 +10:00
Alex Deucher
917f8bc1a8 Add RV740 support 2009-06-11 18:24:41 -04:00
Maciej Cencora
67bbfb9c68 r300: fix VAP setup 
If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang.
 2009-06-11 23:25:54 +02:00
Maciej Cencora
234797564d r300: fix for SW TCL path 
We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order.
We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8.
 2009-06-11 23:25:54 +02:00
Maciej Cencora
8d728b8fe7 r300: don't send unused attributes for SW TCL path 2009-06-11 23:25:54 +02:00
Maciej Cencora
b5d49cb195 r300: send only RS_IP_* regs that we are going to use 2009-06-11 23:25:53 +02:00
Maciej Cencora
2b5f8d2b55 r300: fix RS setup when no colors and textures are sent to FP 
RS_COL_FMT field is part of RS_IP_* reg not RS_INST_*
 2009-06-11 23:25:53 +02:00
Maciej Cencora
34cb4b6be3 r300: r500 fragment program fixes 
- when rewriting per component negate swizzle, first instruction should get not negated source
- KIL instruction ignores swizzles

TODO:
- tex instructions does not support saturation
- tex instructions cannot read from consant memory
 2009-06-11 23:25:53 +02:00
Maciej Cencora
e21e82f425 radeon: increase max bo count 2009-06-11 23:25:53 +02:00
Maciej Cencora
9abc72d1fc r300: fix a GPU lock up 
Sending from VAP more texture coordinates than RS expects results in GPU hang.

Fixes BumpSelfShadow from DirectX8 SDK.
 2009-06-11 23:24:25 +02:00
Maciej Cencora
de19eb0b0d r300: fix vertex program bug 
If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements.

Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests.
 2009-06-11 23:24:25 +02:00
Maciej Cencora
2611e92da5 r300: move some code for easier debugging 2009-06-11 23:24:25 +02:00
Maciej Cencora
52645c4647 r300: print vertex program when debugging is enabled 2009-06-11 23:24:25 +02:00
Maciej Cencora
28724b575d r300: fix output register allocation for vertex shaders 
If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases.
 2009-06-11 23:24:25 +02:00
Maciej Cencora
b4ebd1c191 r300: hw doesn't support saturation for tex instructions 2009-06-11 23:24:25 +02:00
Brian Paul
3754c4135c mesa: rework vertex shader output / fragment shader input attribute matching 
Before, if a vertex shader's outputs didn't exactly match a fragment
shader's inputs we could wind up with invalid TGSI shader declarations.
For example:

Before patch:
DCL OUT[0], POSITION
DCL OUT[1], COLOR[1]
DCL OUT[2], GENERIC[0]
DCL OUT[3], GENERIC[0] <- note duplicate [0]
DCL OUT[4], GENERIC[2]

After patch:
DCL OUT[0], POSITION
DCL OUT[1], COLOR[1]
DCL OUT[2], GENERIC[0]
DCL OUT[3], GENERIC[1]
DCL OUT[4], GENERIC[2]
 2009-06-11 14:58:25 -06:00
Brian Paul
322e8556b9 mesa: add default function for ctx->Driver.CheckQuery() hook 2009-06-11 14:58:25 -06:00
José Fonseca
0ddc38309a python/retrace: Show the contents of the depth/stencil and surfaces before/after transfers. 2009-06-11 20:46:07 +01:00
José Fonseca
e1700009b7 python/retrace: Interpret is_texture_referenced/is_buffer_referenced. 2009-06-11 19:24:48 +01:00
José Fonseca
d5ba39ad08 wgl: Fix prototype. 2009-06-11 19:05:46 +01:00
José Fonseca
877061141a Merge branch 'mesa_7_5_branch' 2009-06-11 19:03:54 +01:00
José Fonseca
de413b1ba9 mesa: Use new pf_is_depth_and_stencil inline. 2009-06-11 19:02:59 +01:00
José Fonseca
3f2e006b75 gallium: New pf_is_depth_and_stencil / pf_is_depth_or_stencil inlines. 2009-06-11 19:02:59 +01:00
José Fonseca
7cafd49c93 mesa: Use PIPE_TEXTURE_USAGE_DEPTH_STENCIL for any depth or stencil format. 2009-06-11 19:02:59 +01:00
José Fonseca
862c7b8cd3 mesa: Remove dead code. 2009-06-11 19:02:59 +01:00
Brian Paul
bb0b954f12 st/mesa: fix typo s/BFC0/BFC1/ 2009-06-11 10:40:19 -06:00
Brian Paul
9d5479eeeb vbo: fix assertion, #define IMM_BUFFER_NAME 
This was sometimes seen when Glean exited upon test failure when using
Gallium.
 2009-06-11 09:46:02 -06:00
José Fonseca
bf89ecb6c9 Merge branch 'mesa_7_5_branch' 
Conflicts:
	src/mesa/state_tracker/st_cb_fbo.c
	src/mesa/state_tracker/st_framebuffer.c
 2009-06-11 16:34:56 +01:00
José Fonseca
cc09724a50 python/tests: Test sampling from a depth texture. 2009-06-11 16:22:17 +01:00
Jakob Bornecrantz
41cf681535 mesa: Only do read write when we don't have a depth value to write 2009-06-11 15:37:53 +01:00
José Fonseca
e3f14f2f3b progs: Port fp programs to GLEW. 2009-06-11 13:19:34 +01:00
José Fonseca
48d816b8ff mesa: Take the format from the right structure. 2009-06-11 12:23:09 +01:00
José Fonseca
96aca15c9d meas: Use a read/write transfer when writing stencil component, but not touching the depth component. 2009-06-11 11:47:20 +01:00
Jerome Glisse
b445e54868 r300: fix indexed primitive rendering when using memory manager 2009-06-11 11:06:14 +02:00
Alex Deucher
1d8d4cad6a Properly set aos_count 
This is used by radeonReleaseArrays to free AOS.
 2009-06-11 01:54:40 -04:00
Thomas Hellstrom
0d2ac7a10b dri st: Don't require the PIPE_TEXTURE_USAGE_RENDER_TARGET property for depth- and stencil renderbuffers. 
Signed-off-by: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
 2009-06-11 00:56:03 +02:00
Michel Dänzer
550a2fe1b7 scons: Indent abbreviated command line strings, so command messages stand out. 
Also add ASPPCOMSTR.
 2009-06-11 12:15:50 +02:00
Michel Dänzer
3885b708fd intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL. 
Fixes glean depthStencil test.
 2009-06-11 12:09:10 +02:00
Alex Deucher
7ac2f655f8 move radeon_set_screen_flags() up so CHIP_FAMILY is set before using it 
fixes last commit.
 2009-06-10 18:02:20 -04:00
Alex Deucher
51507b0e94 Use correct scratch reg offset for r6xx/r7xx 2009-06-10 17:56:05 -04:00