Commit graph

16701 commits

Author SHA1 Message Date
Michel Dänzer
396af00ffe radeonsi: Untiled textures are linear aligned, not linear general.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:38:45 +02:00
Tom Stellard
cebbdd4ac2 radeon/llvm: Cleanup makefile
Hopefully, this will fix all the parallel make problems people have
been having.
2012-09-06 13:30:42 +00:00
Matt Turner
b6109de34f Remove useless checks for NULL before freeing
Same as earlier commit, except for "FREE"

This patch has been generated by the following Coccinelle semantic
patch:

// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it

@@
expression E;
@@
+ FREE (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   FREE(E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
type T;
@@
+ FREE ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   FREE((T) E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
@@
+ FREE (E);
- if (unlikely (E != NULL)) {
-   FREE (E);
- }

@@
expression E;
type T;
@@
+ FREE ((T) E);
- if (unlikely (E != NULL)) {
-   FREE ((T) E);
- }

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner
5067506ea6 Remove useless checks for NULL before freeing
This patch has been generated by the following Coccinelle semantic
patch:

// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it

@@
expression E;
@@
+ free (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   free(E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
type T;
@@
+ free ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   free((T) E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
@@
+ free (E);
- if (unlikely (E != NULL)) {
-   free (E);
- }

@@
expression E;
type T;
@@
+ free ((T) E);
- if (unlikely (E != NULL)) {
-   free ((T) E);
- }

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner
2b7a972e3f Don't cast the return value of malloc/realloc
This patch has been generated by the following Coccinelle semantic
patch:

// Don't cast the return value of malloc/realloc.
//
// Casting the return value of malloc/realloc only stands to hide
// errors.

@@
type T;
expression E1, E2;
@@
- (T)
(
_mesa_align_calloc(E1, E2)
|
_mesa_align_malloc(E1, E2)
|
calloc(E1, E2)
|
malloc(E1)
|
realloc(E1, E2)
)
2012-09-05 22:28:50 -07:00
Matt Turner
7c7b7b068b Remove Xcalloc/Xmalloc/Xfree calls
These calls allowed Xlib to use a custom memory allocator, but Xlib has
used the standard C library functions since at least its initial import
into git in 2003. It seems unlikely that it will grow a custom memory
allocator. The functions now just add extra overhead. Replacing them
will make future Coccinelle patches simpler.

This patch has been generated by the following Coccinelle semantic
patch:

// Remove Xcalloc/Xmalloc/Xfree calls

@@ expression E1, E2; @@
- Xcalloc (E1, E2)
+ calloc (E1, E2)

@@ expression E; @@
- Xmalloc (E)
+ malloc (E)

@@ expression E; @@
- Xfree (E)
+ free (E)

@@ expression E; @@
- XFree (E)
+ free (E)

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:49 -07:00
Vinson Lee
17a574d7cd Use the correct macro _WIN32 for Windows.
The correct predefined macro for Windows is _WIN32, not WIN32 or
__WIN32__.  _WIN32 is defined for 32-bit and 64-bit version of Windows
by both MSVC and MinGW compilers.

http://sourceforge.net/p/predef/wiki/OperatingSystems
http://msdn.microsoft.com/en-us/library/b0084kay.aspx

This patch also fixes a MinGW automake build error.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:14:32 -07:00
Tom Stellard
d220e2de7f radeon/llvm: Fix operand ordering for V_CNDMASK_B32
This fixes several hundred piglit tests.
2012-09-05 13:17:49 -04:00
Tom Stellard
12d3d6f6ab radeon/llvm: Use correct float->int conversion opcode on SI.
V_CVT_I32_F32 converts floats to signed integers, but we were using
V_CVT_F32_I32 which convertes signed integers to float.
2012-09-05 13:17:17 -04:00
Tom Stellard
446d19c12a radeon/llvm: Fix lowering of SI_V_CNDLT
SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.
2012-09-04 14:21:10 -04:00
Tom Stellard
f9fede884b radeon/llvm: Fix encoding of V_CNDMASK_B32
The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register.  This has been fixed by moving the VCC
register to the end of the operand list.
2012-09-04 14:21:10 -04:00
Vincent Lejeune
8eaa36317a radeon/llvm: do not convert f32 operand of select_cc node
v2:-use camel coding style

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:54:37 +02:00
Vincent Lejeune
a4325b3229 radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)
v2:-wrap line at 80 characters

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:54:01 +02:00
Vincent Lejeune
d9e135e18c radeon/llvm: support setcc on f32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:52:53 +02:00
Vincent Lejeune
a383142436 radon/llvm: br_cc f32 now lowered without cast
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:50:44 +02:00
Vincent Lejeune
6a85725f13 radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:44:48 +02:00
Christian König
73dd82061e winsys/radeon: create only one winsys for each fd
Fixing problems with GLAMOR.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-04 10:51:38 +02:00
Christian König
88a4fd8fe6 radeonsi: stop big offsets from hanging the GPU v2
v2: rebased of radeon/llvm fix.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-04 10:51:32 +02:00
Christian König
de7d3825a0 radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTS
So it matches what we really can do.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-04 10:51:26 +02:00
Christian König
8758183f0a radeon/llvm: fix SelectADDR8BitOffset
The offset is unsigned, not signed.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-04 10:51:11 +02:00
José Fonseca
7eb5040197 gallivm,llvmpipe: Use 4-wide vectors on AMD Bulldozer.
8-wide vectors is slower.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2012-09-04 08:49:00 +01:00
Vadim Girlin
f44bda17f5 r600g: adjust QUANT_MODE for higher precision
Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16.

Helps to pass some piglit tests (fbo, multisample).

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-04 00:18:13 +04:00
Vinson Lee
19b3910bd5 util: Add cpuid for Solaris Studio.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-03 12:28:07 -07:00
Christian König
e1673d2001 radeonsi: disable array-textures for now
Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-09-03 11:23:25 +02:00
Christian König
aa5daa61a1 radeonsi: disable Z16 for now
It's causing crashes.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-03 11:23:20 +02:00
Christian König
74a55392b6 radeonsi: disable NPOT textures for now
Looks like we have an alignment issue with NPOT textures
and mipmaps. So disable NPOT textures until we figure out
what is going wrong here.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-03 11:23:14 +02:00
Christian König
e7723b5bdf radeonsi: handle indirect constants gracefully
It's not supported yet, so at least don't try to crash the box.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-03 11:23:08 +02:00
Brian Paul
12bf268aab vega: include u_debug.h for assert() 2012-09-01 09:03:24 -06:00
Brian Paul
fe72a069d1 mesa: s/FREE/free/
v2: replace instances in dri/common/ dirs

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-01 07:47:24 -06:00
Brian Paul
33bb8c051d mesa: s/MALLOC/malloc/
v2: replace instances in dri/common/ dirs

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-01 07:47:24 -06:00
Brian Paul
66d6ba2d83 util: remove u_debug.h from u_math.h
No debug code is used in u_math.h
2012-09-01 07:41:26 -06:00
Brian Paul
a7663729d2 util: include u_debug.h 2012-09-01 07:41:26 -06:00
Brian Paul
b114e37179 tgsi: include u_debug.h 2012-09-01 07:41:26 -06:00
Jakob Bornecrantz
6a7dea93fa dri: Rework planar image interface
As discussed with Kristian on #wayland. Pushes the decision of components into
the dri driver giving it greater freedom to allow t to implement YUV samplers
in hardware, and which mode to use.

This interface will also allow drivers like SVGA to implement YUV surfaces
without the need to sub-allocate and instead send 3 seperate buffers for each
channel, currently not implemented.

I have tested these changes on Gallium Svga. Scott tested them on both intel
and Gallium Radeon. Kristan and Pekka tested them on intel.

v2: Fix typo in dri2_from_planar.
v3: Merge in intel changes.

Tested-by: Scott Moreau <oreaus@gmail.com>
Tested-by: Pekka Paalanen <ppaalanen@gmail.com>
Tested-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
2012-08-31 19:51:02 +02:00
Tom Stellard
022f6d8861 radeon/llvm: Rework how immediate operands are handled with SI
Immediate operands were previously handled in the CodeEmitter, but that
code was buggy and very confusing.  This commit adds a pass that simplifies
the handling of immediate operands by spliting the loading of the
immediate into a sperate insruction that is bundled with the original.
2012-08-31 12:54:58 -04:00
Tom Stellard
1cee70c5d8 radeon/llvm: Fix typo in assert 2012-08-31 12:54:58 -04:00
Tom Stellard
1247549734 radeon/llvm: Fix isEG tablegen predicate
This predicate incorrectly included SI GPUs, so some Evergreen
instructions were being emmitted on SI.
2012-08-31 12:54:58 -04:00
Tom Stellard
ee45dec7c4 radeon/llvm: Add support for RCP instruction on SI 2012-08-31 12:54:58 -04:00
Tom Stellard
fc8b4765d0 radeon/llvm: Support AMDGPUfmin DAG node on SI 2012-08-31 12:54:57 -04:00
Tom Stellard
c3c323a164 radeonsi: Handle TGSI_SEMANTIC_PSIZE
The relevant POINT_SIZE registers are being set using the
pipe_rasterizer_state, so we just need to tell the shader compiler which
export type to use.

This fixes several of the glean glsl tests.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-31 12:53:51 -04:00
Brian Paul
c5f9cf8232 util: add casts to silence signed/unsigned comparison warnings 2012-08-31 08:04:40 -06:00
Marek Olšák
0e470533ad r600g: enable transform feedback on Cayman
There doesn't seem to be anything wrong with it.
2012-08-31 01:19:03 +02:00
Marek Olšák
64db3cc6ad r600g: implement MSAA for Cayman
Everything works except for blitting MSAA colorbuffers, which isn't
so trivial on Cayman. It's a rarely-used feature anyway.
2012-08-31 01:19:03 +02:00
Marek Olšák
c2e9dd0276 r600g: enable MSAA on r6xx by default
DRM 2.22.0 is required though. Also require the new DRM for r700, as
there are some important fixes for that generation too.
2012-08-30 19:43:56 +02:00
Marek Olšák
2f6eb3afb7 r600g: disable MSAA depth decompression on r6xx 2012-08-30 19:43:56 +02:00
Marek Olšák
78354011f9 r600g: implement color resolve for r600
The blend state is different and the resolve single-sample buffer must have
FMASK and CMASK enabled. I decided to have one CMASK and one FMASK
per context instead of per resource.

There are new FMASK and CMASK allocation helpers and a new buffer_create
helper for that.
2012-08-30 19:43:56 +02:00
Marek Olšák
863e2c85b9 r600g: fix CB_SHADER_MASK and CB_TARGET_MASK for r6xx 2012-08-30 19:43:56 +02:00
Marek Olšák
187d7fb2fe r600g: implement draw_rectangle callback
The color resolve on r6xx needs PT_RECTLIST. Using conventional primitive
types (triangles and quads) produces an ugly line between two diagonally
opposite corners. I guess a rectangular point sprite would work too.
2012-08-30 19:43:55 +02:00
Marek Olšák
8698a3b85d r600g: implement MSAA for r700
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-30 19:43:55 +02:00
Marek Olšák
edf22a5c6d r600g: change programming of CB_SHADER_MASK on r600-r700
This one actually makes more sense and gives the expected value
for MSAA resolve.

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-30 19:43:55 +02:00