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radeon/llvm: support setcc on f32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
parent
a383142436
commit
d9e135e18c
1 changed files with 27 additions and 9 deletions
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@ -47,7 +47,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::f32, Custom);
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setSchedulingPreference(Sched::VLIW);
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}
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@ -519,14 +519,32 @@ SDValue R600TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const
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SDValue CC = Op.getOperand(2);
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DebugLoc DL = Op.getDebugLoc();
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assert(Op.getValueType() == MVT::i32);
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Cond = DAG.getNode(
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ISD::SELECT_CC,
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Op.getDebugLoc(),
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MVT::i32,
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LHS, RHS,
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DAG.getConstant(-1, MVT::i32),
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DAG.getConstant(0, MVT::i32),
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CC);
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if (LHS.getValueType() == MVT::i32) {
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Cond = DAG.getNode(
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ISD::SELECT_CC,
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Op.getDebugLoc(),
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MVT::i32,
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LHS, RHS,
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DAG.getConstant(-1, MVT::i32),
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DAG.getConstant(0, MVT::i32),
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CC);
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} else if (LHS.getValueType() == MVT::f32) {
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Cond = DAG.getNode(
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ISD::SELECT_CC,
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Op.getDebugLoc(),
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MVT::f32,
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LHS, RHS,
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DAG.getConstantFP(1.0f, MVT::f32),
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DAG.getConstantFP(0.0f, MVT::f32),
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CC);
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Cond = DAG.getNode(
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ISD::FP_TO_SINT,
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DL,
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MVT::i32,
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Cond);
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} else {
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assert(0 && "Not valid type for set_cc");
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}
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Cond = DAG.getNode(
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ISD::AND,
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DL,
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