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r600g: implement color resolve for r600
The blend state is different and the resolve single-sample buffer must have FMASK and CMASK enabled. I decided to have one CMASK and one FMASK per context instead of per resource. There are new FMASK and CMASK allocation helpers and a new buffer_create helper for that.
This commit is contained in:
Marek Olšák
parent
863e2c85b9
commit
78354011f9
7 changed files with 200 additions and 27 deletions
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@ -237,12 +237,11 @@ bool r600_init_resource(struct r600_screen *rscreen,
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}
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struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
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const struct pipe_resource *templ)
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const struct pipe_resource *templ,
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unsigned alignment)
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{
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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struct r600_resource *rbuffer;
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/* XXX We probably want a different alignment for buffers and textures. */
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unsigned alignment = 4096;
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rbuffer = MALLOC_STRUCT(r600_resource);
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@ -156,6 +156,9 @@ static void r600_destroy_context(struct pipe_context *context)
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{
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struct r600_context *rctx = (struct r600_context *)context;
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pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
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pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
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if (rctx->no_blend) {
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rctx->context.delete_blend_state(&rctx->context, rctx->no_blend);
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}
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@ -250,7 +253,8 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
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if (r600_context_init(rctx))
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goto fail;
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rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
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rctx->custom_blend_resolve = r600_create_resolve_blend(rctx);
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rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
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: r600_create_resolve_blend(rctx);
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rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
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rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
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rctx->family == CHIP_RV620 ||
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@ -450,6 +450,13 @@ struct r600_context {
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/* Index buffer. */
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struct pipe_index_buffer index_buffer;
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/* Dummy CMASK and FMASK buffers used to get around the R6xx hardware
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* bug where valid CMASK and FMASK are required to be present to avoid
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* a hardlock in certain operations but aren't actually used
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* for anything useful. */
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struct r600_resource *dummy_fmask;
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struct r600_resource *dummy_cmask;
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};
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static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
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@ -518,7 +525,8 @@ bool r600_init_resource(struct r600_screen *rscreen,
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unsigned size, unsigned alignment,
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unsigned bind, unsigned usage);
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struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
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const struct pipe_resource *templ);
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const struct pipe_resource *templ,
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unsigned alignment);
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/* r600_pipe.c */
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void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
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@ -552,6 +560,7 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad
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void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
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void *r600_create_db_flush_dsa(struct r600_context *rctx);
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void *r600_create_resolve_blend(struct r600_context *rctx);
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void *r700_create_resolve_blend(struct r600_context *rctx);
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void *r600_create_decompress_blend(struct r600_context *rctx);
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void r600_polygon_offset_update(struct r600_context *rctx);
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void r600_adjust_gprs(struct r600_context *rctx);
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@ -31,7 +31,7 @@ static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
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return r600_compute_global_buffer_create(screen, templ);
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}
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else {
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return r600_buffer_create(screen, templ);
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return r600_buffer_create(screen, templ, 4096);
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}
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} else {
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return r600_texture_create(screen, templ);
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@ -64,6 +64,18 @@ struct r600_texture {
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#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
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struct r600_fmask_info {
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unsigned size;
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unsigned alignment;
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unsigned bank_height;
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};
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struct r600_cmask_info {
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unsigned size;
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unsigned alignment;
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unsigned slice_tile_max;
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};
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struct r600_surface {
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struct pipe_surface base;
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@ -88,6 +100,8 @@ struct r600_surface {
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unsigned cb_color_cmask; /* CB_COLORn_CMASK (EG) or CB_COLORn_TILE (r600) */
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unsigned cb_color_cmask_slice; /* EG only */
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unsigned cb_color_mask; /* R600 only */
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struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
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struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
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/* DB registers. */
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unsigned db_depth_info; /* DB_Z_INFO (EG) or DB_DEPTH_INFO (r600) */
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@ -104,6 +118,13 @@ void r600_resource_destroy(struct pipe_screen *screen, struct pipe_resource *res
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void r600_init_screen_resource_functions(struct pipe_screen *screen);
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/* r600_texture */
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void r600_texture_get_fmask_info(struct r600_screen *rscreen,
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struct r600_texture *rtex,
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unsigned nr_samples,
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struct r600_fmask_info *out);
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void r600_texture_get_cmask_info(struct r600_screen *rscreen,
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struct r600_texture *rtex,
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struct r600_cmask_info *out);
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struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
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const struct pipe_resource *templ);
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struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
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@ -1232,9 +1232,31 @@ static void r600_set_viewport_state(struct pipe_context *ctx,
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r600_context_pipe_state_set(rctx, rstate);
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}
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static void r600_init_color_surface(struct r600_context *rctx,
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struct r600_surface *surf)
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static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
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unsigned size, unsigned alignment)
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{
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struct pipe_resource buffer;
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memset(&buffer, 0, sizeof buffer);
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buffer.target = PIPE_BUFFER;
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buffer.format = PIPE_FORMAT_R8_UNORM;
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buffer.bind = PIPE_BIND_CUSTOM;
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buffer.usage = PIPE_USAGE_STATIC;
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buffer.flags = 0;
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buffer.width0 = size;
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buffer.height0 = 1;
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buffer.depth0 = 1;
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buffer.array_size = 1;
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return (struct r600_resource*)
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r600_buffer_create(&rscreen->screen, &buffer, alignment);
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}
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static void r600_init_color_surface(struct r600_context *rctx,
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struct r600_surface *surf,
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bool force_cmask_fmask)
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{
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struct r600_screen *rscreen = rctx->screen;
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struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
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unsigned level = surf->base.u.tex.level;
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unsigned pitch, slice;
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@ -1366,11 +1388,18 @@ static void r600_init_color_surface(struct r600_context *rctx,
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}
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}
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/* These might not always be initialized to zero. */
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surf->cb_color_base = offset >> 8;
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surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
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S_028060_SLICE_TILE_MAX(slice);
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surf->cb_color_fmask = surf->cb_color_base;
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surf->cb_color_cmask = surf->cb_color_base;
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surf->cb_color_mask = 0;
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pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
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&rtex->resource.b.b);
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pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
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&rtex->resource.b.b);
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if (rtex->cmask_size) {
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surf->cb_color_cmask = rtex->cmask_offset >> 8;
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@ -1383,7 +1412,56 @@ static void r600_init_color_surface(struct r600_context *rctx,
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} else { /* cmask only */
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color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
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}
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} else if (force_cmask_fmask) {
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/* Allocate dummy FMASK and CMASK if they aren't allocated already.
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*
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* R6xx needs FMASK and CMASK for the destination buffer of color resolve,
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* otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
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* because it's not an MSAA buffer.
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*/
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struct r600_cmask_info cmask;
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struct r600_fmask_info fmask;
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r600_texture_get_cmask_info(rscreen, rtex, &cmask);
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r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
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/* CMASK. */
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if (!rctx->dummy_cmask ||
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rctx->dummy_cmask->buf->size < cmask.size ||
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rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
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struct pipe_transfer *transfer;
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void *ptr;
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pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
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rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
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/* Set the contents to 0xCC. */
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ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
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memset(ptr, 0xCC, cmask.size);
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pipe_buffer_unmap(&rctx->context, transfer);
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}
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pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
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&rctx->dummy_cmask->b.b);
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/* FMASK. */
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if (!rctx->dummy_fmask ||
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rctx->dummy_fmask->buf->size < fmask.size ||
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rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
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pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
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rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
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}
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pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
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&rctx->dummy_fmask->b.b);
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/* Init the registers. */
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color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
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surf->cb_color_cmask = 0;
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surf->cb_color_fmask = 0;
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surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
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S_028100_FMASK_TILE_MAX(slice);
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}
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surf->cb_color_info = color_info;
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if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
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@ -1509,6 +1587,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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struct r600_resource *res;
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struct r600_texture *rtex;
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uint32_t tl, br, i, nr_samples, max_dist;
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bool is_resolve = state->nr_cbufs == 2 &&
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state->cbufs[0]->texture->nr_samples > 1 &&
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state->cbufs[1]->texture->nr_samples <= 1;
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/* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
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bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
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if (rstate == NULL)
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return;
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@ -1528,12 +1611,17 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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rctx->compressed_cb_mask = 0;
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for (i = 0; i < state->nr_cbufs; i++) {
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bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
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surf = (struct r600_surface*)state->cbufs[i];
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res = (struct r600_resource*)surf->base.texture;
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rtex = (struct r600_texture*)res;
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if (!surf->color_initialized) {
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r600_init_color_surface(rctx, surf);
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if (!surf->color_initialized || force_cmask_fmask) {
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r600_init_color_surface(rctx, surf, force_cmask_fmask);
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if (force_cmask_fmask) {
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/* re-initialize later without compression */
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surf->color_initialized = false;
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}
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}
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if (!surf->export_16bpc) {
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@ -1549,9 +1637,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
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surf->cb_color_view);
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r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
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surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
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surf->cb_color_fmask, surf->cb_buffer_fmask,
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RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
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surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
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surf->cb_color_cmask, surf->cb_buffer_cmask,
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RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
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surf->cb_color_mask);
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@ -1607,9 +1697,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
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/* If we're doing MSAA resolve... */
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if (state->nr_cbufs == 2 &&
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state->cbufs[0]->texture->nr_samples > 1 &&
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state->cbufs[1]->texture->nr_samples <= 1) {
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if (is_resolve) {
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r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
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} else {
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/* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
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@ -2551,6 +2639,28 @@ void r600_fetch_shader(struct pipe_context *ctx,
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}
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void *r600_create_resolve_blend(struct r600_context *rctx)
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{
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struct pipe_blend_state blend;
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struct r600_pipe_state *rstate;
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unsigned i;
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memset(&blend, 0, sizeof(blend));
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blend.independent_blend_enable = true;
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for (i = 0; i < 2; i++) {
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blend.rt[i].colormask = 0xf;
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blend.rt[i].blend_enable = 1;
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blend.rt[i].rgb_func = PIPE_BLEND_ADD;
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blend.rt[i].alpha_func = PIPE_BLEND_ADD;
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blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
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blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
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blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
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blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
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}
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rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
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return rstate;
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}
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void *r700_create_resolve_blend(struct r600_context *rctx)
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{
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struct pipe_blend_state blend;
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struct r600_pipe_state *rstate;
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@ -252,13 +252,15 @@ static const struct u_resource_vtbl r600_texture_vtbl =
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NULL /* transfer_inline_write */
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};
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static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
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struct r600_texture *rtex)
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/* The number of samples can be specified independently of the texture. */
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void r600_texture_get_fmask_info(struct r600_screen *rscreen,
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struct r600_texture *rtex,
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unsigned nr_samples,
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struct r600_fmask_info *out)
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{
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/* FMASK is allocated pretty much like an ordinary texture.
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* Here we use bpe in the units of bits, not bytes. */
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struct radeon_surface fmask = rtex->surface;
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unsigned nr_samples = rtex->resource.b.b.nr_samples;
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switch (nr_samples) {
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case 2:
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@ -297,10 +299,23 @@ static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
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}
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assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
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out->bank_height = fmask.bankh;
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out->alignment = MAX2(256, fmask.bo_alignment);
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out->size = (fmask.bo_size + 7) / 8;
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}
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static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
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struct r600_texture *rtex)
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{
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struct r600_fmask_info fmask;
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r600_texture_get_fmask_info(rscreen, rtex,
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rtex->resource.b.b.nr_samples, &fmask);
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/* Reserve space for FMASK while converting bits back to bytes. */
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rtex->fmask_bank_height = fmask.bankh;
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rtex->fmask_offset = align(rtex->size, MAX2(256, fmask.bo_alignment));
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rtex->fmask_size = (fmask.bo_size + 7) / 8;
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rtex->fmask_bank_height = fmask.bank_height;
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rtex->fmask_offset = align(rtex->size, fmask.alignment);
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rtex->fmask_size = fmask.size;
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rtex->size = rtex->fmask_offset + rtex->fmask_size;
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#if 0
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printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
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@ -308,8 +323,9 @@ static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
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#endif
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}
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static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
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struct r600_texture *rtex)
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void r600_texture_get_cmask_info(struct r600_screen *rscreen,
|
||||
struct r600_texture *rtex,
|
||||
struct r600_cmask_info *out)
|
||||
{
|
||||
unsigned cmask_tile_width = 8;
|
||||
unsigned cmask_tile_height = 8;
|
||||
|
|
@ -331,14 +347,25 @@ static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
|
|||
unsigned base_align = num_pipes * pipe_interleave_bytes;
|
||||
unsigned slice_bytes =
|
||||
((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
|
||||
unsigned size = rtex->surface.array_size * align(slice_bytes, base_align);
|
||||
|
||||
assert(macro_tile_width % 128 == 0);
|
||||
assert(macro_tile_height % 128 == 0);
|
||||
|
||||
rtex->cmask_slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
|
||||
rtex->cmask_offset = align(rtex->size, MAX2(256, base_align));
|
||||
rtex->cmask_size = size;
|
||||
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
|
||||
out->alignment = MAX2(256, base_align);
|
||||
out->size = rtex->surface.array_size * align(slice_bytes, base_align);
|
||||
}
|
||||
|
||||
static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
|
||||
struct r600_texture *rtex)
|
||||
{
|
||||
struct r600_cmask_info cmask;
|
||||
|
||||
r600_texture_get_cmask_info(rscreen, rtex, &cmask);
|
||||
|
||||
rtex->cmask_slice_tile_max = cmask.slice_tile_max;
|
||||
rtex->cmask_offset = align(rtex->size, cmask.alignment);
|
||||
rtex->cmask_size = cmask.size;
|
||||
rtex->size = rtex->cmask_offset + rtex->cmask_size;
|
||||
#if 0
|
||||
printf("CMASK: macro tile width = %u, macro tile height = %u, "
|
||||
|
|
@ -479,6 +506,9 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
|
|||
static void r600_surface_destroy(struct pipe_context *pipe,
|
||||
struct pipe_surface *surface)
|
||||
{
|
||||
struct r600_surface *surf = (struct r600_surface*)surface;
|
||||
pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
|
||||
pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
|
||||
pipe_resource_reference(&surface->texture, NULL);
|
||||
FREE(surface);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue