Commit graph

50508 commits

Author SHA1 Message Date
Michel Dänzer
36d2914a19 radeonsi: Fix vertex buffer resource for stride 0. 2012-05-10 13:54:27 +02:00
Tom Stellard
788fd04dac radeon/llvm: Remove AMDGPUConstants.pm 2012-05-09 12:49:44 -04:00
Tom Stellard
c2e081030e radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const 2012-05-09 12:49:44 -04:00
Tom Stellard
d0403cafd4 radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate 2012-05-09 12:49:44 -04:00
Brian Paul
a1c5513c17 svga: implement CEIL opcode translation
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-05-09 10:53:15 -06:00
Christoph Bumiller
f7665ca4fc glsl_to_tgsi: use TGSI_OPCODE_CEIL for ir_unop_ceil
The implementation using FLR was buggy, the second negation could
get lost.
2012-05-09 17:13:14 +02:00
Christoph Bumiller
6ae12bac59 gallium/drivers: handle TGSI_OPCODE_CEIL 2012-05-09 17:09:30 +02:00
Kai Wasserbäch
8c98635d4f r600g: Handle TGSI_OPCODE_CEIL (v2)
v2: Enabled CEIL on Cayman too.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-09 09:40:16 -04:00
Dave Airlie
729d914824 gallivm: implement iabs/issg opcode.
Reimplemented by Olivier Galibert <galibert@pobox.com>

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-09 08:26:55 +01:00
Yuanhan Liu
f939776cb2 i965: fix wrong cube/3D texture layout
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.

From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
   All of the LOD=0 q-planes are stacked vertically, then below that,
   the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
   stacked four-wide below that, and so on.

Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.

This would fix the following webgl test case on all gen4 platforms:
  conformance/textures/texture-size-cube-maps.html

NOTE: This is a candidate for stable release branches.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2012-05-09 15:13:56 +08:00
Tom Stellard
5aaaa6a426 radeon/llvm: Remove AMDILUtilityFunctions.cpp 2012-05-08 15:47:46 -04:00
Tom Stellard
21ab46eae8 radeon/llvm: Remove some unused functions from AMDILInstrInfo 2012-05-08 15:47:46 -04:00
Tom Stellard
f903da7335 radeon/llvm: Add some comments and fix coding style 2012-05-08 15:47:46 -04:00
Tom Stellard
a8d82c44f7 radeon/llvm: Remove the EXPORT_REG instruction 2012-05-08 15:47:46 -04:00
Tom Stellard
8a4c25dd7e radeon/llvm: Use a custom inserter to lower RESERVE_REG 2012-05-08 15:47:46 -04:00
Tom Stellard
94e797d0fa radeon/llvm: Use a custom inserter to lower STORE_OUTPUT 2012-05-08 15:47:46 -04:00
Tom Stellard
4226433625 radeon/llvm: Remove AMDGPULowerShaderInstructions class
It is no longer used.
2012-05-08 15:47:46 -04:00
Tom Stellard
ad385c402e radeon/llvm: Use a custom inserter to lower LOAD_INPUT 2012-05-08 15:47:45 -04:00
Tom Stellard
52a7f212d3 radeon/llvm: Remove the ReorderPreloadInstructions pass 2012-05-08 15:47:45 -04:00
Tom Stellard
e042b3aeed radeon/llvm: Remove old comment from AMDIL.h 2012-05-08 15:47:45 -04:00
Paul Berry
e19741c4d8 Add bin/compile to .gitignore
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-08 13:10:00 -07:00
Olivier Galibert
363c14ae0c glsl: Change built-in constant expression evaluation to run the IR.
This removes code duplication with
ir_expression::constant_expression_value and builtins/ir/*.

Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-08 12:55:52 -07:00
Olivier Galibert
2ff7b121ca glsl: Add an origin pointer in the function signature object.
This points to the object with the function body, allowing us to map
from a built-in prototype to the actual body with IR code to execute.

Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-08 12:55:52 -07:00
Olivier Galibert
8ec01ba2ff glsl: Add methods to copy parts of one ir_constant into another.
- copy_masked_offset copies part of a constant into another,
  assign-like.

- copy_offset copies a constant into (a subset of) another,
  funcall-return like.

These methods are to be used to trace through assignments and function
calls when computing a constant expression.

Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
2012-05-08 12:55:50 -07:00
Olivier Galibert
a270e86d38 glsl: Add a constant_referenced method to ir_dereference*
The method is used to get a reference to an ir_constant * within the
context of evaluating an assignment when calculating a
constant_expression_value.

Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
2012-05-08 12:55:47 -07:00
Olivier Galibert
6e4852a3a5 glsl: Add a variable context to constant_expression_value().
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
2012-05-08 12:55:46 -07:00
Olivier Galibert
27a198388e glsl: Extend ir_constant::zero to handle more types.
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
2012-05-08 12:55:38 -07:00
Kenneth Graunke
f72e9b2041 glsl: Fix broken constant expression handling for <, <=, >, and >=.
We were looping over all the vector components, but only dealing with
the first one.  This was masked by the fact that constant expression
handling on built-ins went through custom code for the lessThan()
/function/ rather than the ir_binop_less expression operator.

NOTE: This is a candidate for all release branches.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-08 12:28:44 -07:00
Brian Paul
c55ebc3e3e vbo: add some comments 2012-05-08 12:12:03 -06:00
Brian Paul
ad5e3609d4 mesa: remove needless casts in save_EdgeFlag() 2012-05-08 12:12:03 -06:00
Brian Paul
2428de1c50 mesa: minor clean-ups in dlist material code 2012-05-08 12:12:03 -06:00
Brian Paul
b13ecbadea mesa: fix error strings in dlist code 2012-05-08 12:12:03 -06:00
Marek Olšák
c5e473fbe2 mesa: add gl_context::NewDriverState and use it for vertex arrays
The vbo module recomputes its states if _NEW_ARRAY is set, so it shouldn't use
the same flag to notify the driver. Since we've run out of bits in NewState
and NewState is for core Mesa anyway, we need to find another way.

This patch is the first to start decoupling the state flags meant only
for core Mesa and those only for drivers.

The idea is to have two flag sets:
- gl_context::NewState - used by core Mesa only
- gl_context::NewDriverState - used by drivers only (the flags are defined
                               by the driver and opaque to core Mesa)

It makes perfect sense to use NewState|=_NEW_ARRAY to notify the vbo module
that the user changed vertex arrays, and the vbo module in turn sets
a driver-specific flag to notify the driver that it should update its vertex
array bindings.

The driver decides which bits of NewDriverState should be set and stores them
in gl_context::DriverFlags. Then, Core Mesa can do this:
ctx->NewDriverState |= ctx->DriverFlags.NewArray;

This patch implements this behavior and adapts st/mesa.
DriverFlags.NewArray is set to ST_NEW_VERTEX_ARRAYS.

Core Mesa only sets NewDriverState. It's the driver's responsibility to read
it whenever it wants and reset it to 0.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-05-08 15:57:51 +02:00
Marek Olšák
50f7e75f9e mesa: move gl_client_array*[] from vbo_draw_func into gl_context
In the future we'd like to treat vertex arrays as a state and
not as a parameter to the draw function. This is the first step
towards that goal. Part of the goal is to avoid array re-validation
for every draw call.

This commit adds:
const struct gl_client_array **gl_context::Array::_DrawArrays.

The pointer is changed in:
* vbo_draw_method
* vbo_rebase_prims - unused by gallium
* vbo_split_prims - unused by gallium
* st_RasterPos

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-05-08 15:57:51 +02:00
Marek Olšák
a7ac9c9c7d vbo: move vbo_draw_method into vbo_context.h
I'll need vbo_context in that function soon.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-05-08 15:57:51 +02:00
Vadim Girlin
d6aa7cd7f8 radeon/llvm: add suport for cube textures
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:23 +04:00
Vadim Girlin
e98e209528 radeon/llvm: add support for CUBE ALU instruction
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:23 +04:00
Vadim Girlin
996fa375ec radeon/llvm: add support for some ALU instructions
Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG,
I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX,
IMIN, IMAX, UMIN, UMAX

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:23 +04:00
Vadim Girlin
e9be193430 radeon/llvm: add missing cases for BREAK/CONTINUE
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
e740b60845 radeon/llvm: add support for AHSR/LSHR/LSHL instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
95ed0e9b6b radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
d8a1204854 radeon/llvm: add support for VertexID, InstanceID
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
e3e7ae732c radeon/llvm: fix live-in handling for inputs
Set the input registers as live-in for entry basic block.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
757f471ba9 radeon/llvm: add support for v4i32
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
06db74a753 radeon/llvm: fix ABS_i32 instruction lowering
Swap source operands.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
3a6a1cd75f radeon/llvm: use integer comparison for IF
Replacing "float equal to 1.0f" with "int not equal to 0".
This should help for further optimization of boolean computations.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:22 +04:00
Vadim Girlin
2a88dfc521 radeon/llvm: use bitcasts for integers
We're using float as default type, so basically for every instruction that
wants other types for dst/src operands we need to perform the bitcast
to/from default float. Currently bitcast produces no-op MOV instruction,
will be eliminated later.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-05-08 01:18:21 +04:00
Tom Stellard
3f8c37967a r600g: Fix out of tree builds that use the LLVM backend
https://bugs.freedesktop.org/show_bug.cgi?id=49567
2012-05-07 15:05:25 -04:00
Tom Stellard
c425c3823f radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()
These weren't being used at all and they were causing build failures
when LLVM was built with NDEBUG defined and mesa was not.

https://bugs.freedesktop.org/show_bug.cgi?id=49110
2012-05-07 14:01:53 -04:00
Paul Berry
714b4f6184 i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen7, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0.  Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4.  When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.

As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0.  This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.

Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.

Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
2012-05-07 10:50:33 -07:00