fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 00:49:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965: fix wrong cube/3D texture layout

Browse source 
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.

From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
   All of the LOD=0 q-planes are stacked vertically, then below that,
   the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
   stacked four-wide below that, and so on.

Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.

This would fix the following webgl test case on all gen4 platforms:
  conformance/textures/texture-size-cube-maps.html

NOTE: This is a candidate for stable release branches.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
This commit is contained in:
Yuanhan Liu 2012-05-02 17:29:11 +08:00
parent 5aaaa6a426
commit f939776cb2
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/mesa/drivers/dri/i965/brw_tex_layout.c
View file

@ -115,6 +115,8 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
intel_miptree_set_image_offset(mt, level, q, x, y);
x += pack_x_pitch;
}
if (x > mt->total_width)
mt->total_width = x;
x = 0;
y += pack_y_pitch;
@ -135,10 +137,9 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
pack_x_nr <<= 1;
}
} else {
pack_x_nr <<= 1;
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
pack_x_nr <<= 1;
assert(pack_x_pitch * pack_x_nr <= mt->total_width);
}
if (pack_y_pitch > 2) {